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HT46RU66/HT46CU66 A/D with LCD Type 8-Bit MCU
Technical Document
* Tools Information * FAQs * Application Note - HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM - HA0004E HT48 & HT46 MCU UART Software Implementation Method - HA0005E Controlling the I2C bus with the HT48 & HT46 MCU Series - HA0047E An PWM application example using the HT46 series of MCUs
Features
* Operating voltage: * 8-bit RTC prescaler * Watchdog Timer * Buzzer output function * Crystal, RC and 32768Hz crystal system oscillator
fSYS=4MHz: 2.2V~5.5V fSYS=8MHz: 3.3V~5.5V
* 32 bidirectional I/O lines * Two external interrupt inputs * Two 16-bit programmable timer/event counters with
option
* Power down and wake-up functions reduce power
Programmable Frequency Divider, PFD, function
* One 8-bit programmable timer/event counter with
consumption
* 16-level subroutine nesting * 8-channel 12-bit resolution A/D converter * 4-channel PWM output shared with 4 I/O lines * Bit manipulation instruction * 16-bit table read instruction * Up to 0.5ms instruction cycle with 8MHz system clock * 63 powerful instructions * Instruction execution within 1 or 2 machine cycles * Low voltage reset/detector function * 52-pin QFP, 56-pin SSOP, 100-pin QFP packages
source clock prescaler
* 473 or 464 segment LCD driver with logic
output option for SEG0~SEG23)
* 16K16 program memory * 5768 data memory RAM * Universal Asynchronous Receiver Transmitter
(UART)
* PFD function for sound generation * Real Time Clock - RTC
General Description
The HT46RU66/HT46CU66 are 8-bit, high performance, RISC architecture microcontroller devices specifically designed for A/D product applications that interface directly to analog signals and which require an LCD Interface. The HT46CU66 mask version device, is fully pin and functionally compatible with its sister HT46RU66 OTP device. The advantages of low power consumption, I/O flexibility, timer functions, oscillator options, multi-channel A/D Converter, Pulse Width Modulation function, Power Down and Wake-up functions, in addition to a flexible and configurable LCD interface enhance the versatility of these devices to control a wide range of applications requiring analog signal processing and LCD interfacing, such as electronic metering, environmental monitoring, handheld measurement tools, motor driving, etc. for both the industrial and home appliance application areas. The HT46CU66 is under development and will be available soon.
Rev. 1.00
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HT46RU66/HT46CU66
Block Diagram
In te rru p t C ir c u it P ro g ra m EPROM P ro g ra m C o u n te r STACK IN T C
TM R2C TM R2
M U
P r e s c a le r X TM R2
fS
YS
TM R0C TM R0 PFD0 In s tr u c tio n R e g is te r MP M U X DATA M e m o ry TM R1C TM R1 PFD1 M U X
M U
P r e s c a le r X P D 6 /T M R 0 P D 7 /T M R 1 fS Y S /4 32768Hz
fS
YS
RTC In s tr u c tio n D ecoder ALU T im in g G e n e r a tio n S h ifte r MUX W DT STATUS T im e B a s e PW M PDC OSC2 OSC4 OS RE VD VS OS S C1 S D ACC BP PD P o rt D M U X
fS
YS
/4 RTC OSC OSC3 OSC4
W DT OSC PD PD PD PD PD 0 /P 4 /IN 5 /IN 6 /T 7 /T W M 0 ~ P D 3 /P W M 3 T0 T1 MR0 MR1
C3 L C D D r iv e r
LCD M e m o ry
UART PCC PC 8 -C h a n n e l A /D C o n v e rte r P o rt C PC PC PC PC 0 /T 1~ 6 /T 7 /R MR2 PC5 X X
C O M 0~ COM2
C O M 3/ SEG 46 E N /D IS
SEG 0~ SEG 45 H ALT
PBC PB PAC
P o rt B
P B 0 /A N 0 ~ P B 7 /A N 7 PA PA PA PA PA 0 /B 1 /B 2 3 /P 4~P Z Z FD A7
P o rt A
L V D /L V R
PA
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HT46RU66/HT46CU66
Pin Assignment
SEG SEG SEG SEG SEG SEG SEG OSC OSC VD VRE AVD OSC OSC RE P A 0 /B P A 1 /B PA P A 3 /P F PA
P A 0 /B Z 1 2 3 4 5 6 7 8 9 P A 1 /B Z PA2 P A 3 /P F D PA4 PA5 PA6 PA7 P C 6 /T X P C 7 /R X P B 0 /A N 0 P B 1 /A N 1 P B 2 /A N 2 P B 3 /A N 3 VSS P D 0 /P W M 0 P D 1 /P W M 1 P D 2 /P W M 2 P D 4 /IN T 0 P D 5 /IN T 1 P D 6 /T M R 0 VLCD VMAX V1 V2 C1 C2 COM0
56 55 54 53 52 51 50 49 48 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
RES OSC1 OSC2 VDD OSC3 OSC4 SEG 16 SEG 17 SEG 18 SEG 19 SEG 20 SEG 21 SEG 22 SEG 23 SEG 24 SEG 25 SEG 26 SEG 27 SEG 28 P P P P SEG 29 SEG 30 SEG 31 SEG 32 SEG 33 SEG 34 C O M 3 /S E G 4 6 COM2 COM1 P P P PA5 PA6 PA7 PC4 PC5 P C 6 /T X P C 7 /R X P B 0 /A N 0 P B 1 /A N 1 P B 2 /A N 2 P B 3 /A N 3 P B 4 /A N 4 P B 5 /A N 5 P B 6 /A N 6 P B 7 /A N 7 VSS AVSS D 0 /P W M 0 D 1 /P W M 1 D 2 /P W M 2 D 3 /P W M 3 P D 4 /IN T 0 P D 5 /IN T 1 D 6 /T M R 0 D 7 /T M R 1 C 0 /T M R 2 PC1 PC2 PC3 NC
1 2 3 4 5 6 7 8 9
D
D
100 99 98 97 96 9594 93 92 91 90 89 88 87 86 8584 83 82 81
D S Z F 1 3 4 0 1 2 3 4 5 6 2 2
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 4445 46 4748 49 50
Z
4
80 79 78 77 76 75 74 73 72 71 70 69 68 67
H T 4 6 R U 6 6 /H T 4 6 C U 6 6 1 0 0 Q F P -A
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
SEG SEG SEG SEG SEG NC SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG 8 9
7 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG COM COM COM COM C2 C1 V2 V1 VMA VLC D 36 37 38 39 40 41 42 43 44 45 3 /S E G 4 6 X 0 1 2
H T 4 6 R U 6 6 /H T 4 6 C U 6 6 5 6 S S O P -A
SEG1 SEG1 OSC OSC VD OSC OSC RE P A 0 /B P A 1 /B PA P A 3 /P F PA PA5 PA6 PA7 6 /T X 7 /R X /A N 0 /A N 1 /A N 2 /A N 3 VSS WM0 WM1 WM2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 42 41 40
D S Z 1 2 3 4 4
39 38 37 36 35 34 33 32 31 30 29 28 27
D
Z 2 SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG 18 19 20 21 22 23 24 25 26 27 28 29 30 6 7
P
P
P
P
PC PC B0 B1 B2 B3
H T 4 6 R U 6 6 /H T 4 6 C U 6 6 5 2 Q F P -A
P D 0 /P P D 1 /P P D 2 /P
SE SE SE CO CO CO CO V1 VM VL PD PD PD AX CD 6 /T M R 0 5 /IN T 1 4 /IN T 0 G3 G3 G3 M3 3 2 1 /S E G 4 6 M0 M1 M2
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Pin Description
Pin Name PA0/BZ PA1/BZ PA2 PA3/PFD PA4~PA7 I/O Configuration Option Pull-high Wake-up Buzzer PFD Description Bidirectional 8-bit input/output port. Each individual pin on this port can be configured as a wake-up input by a configuration option. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine which pins on the port have pull-high resistors. Pins PA0, PA1 and PA3 are pin-shared with BZ, BZ and PFD respectively, the function of which is chosen via configuration options. Bidirectional 8-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine which pins on the port have pull-high resistors. PB is pin-shared with the A/D input pins. The A/D inputs are selected via software instructions. Once selected as an A/D input, the I/O function and pull-high resistor functions are disabled automatically. Bidirectional 8-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. A Configuration option determines if the port has pull-high resistors. Pin PC0 is pin-shared with the timer input pin TMR2. Pins PC6 and PC7 are pin-shared with the UART pins TX and RX. Bidirectional 8-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine which pins on the port have pull-high resistors. PD0~PD3 are pin-shared with PWM0~PWM3, the function of each pin is selected via a configuration option. Pins PD4 and PD5 are pin-shared with external interrupt input pins INT0 and INT1 respectively. Configuration options determine the interrupt enable/disable and the interrupt low/high trigger type. Pins PD6 and PD7 are pin-shared with the external timer input pins TMR0 and TMR1 respectively. OSC1 and OSC2 are connected to an external RC network or external crystal, determined by configuration option, for the internal system clock. For external RC system clock operation, OSC2 is an output pin where the system frequency can be monitored, at a frequency of 1/4 system clock. If an RTC oscillator on pins OSC3 and OSC4 is used as a system clock, then the OSC1 and OSC2 pins should be left floating. OSC3 and OSC4 are connected to a 32768Hz crystal to form a real time clock for timing purposes or to form a system clock. LCD power supply IC maximum voltage, connect to VDD, VLCD or V1 LCD voltage pump LCD driver outputs for LCD panel segments. A configuration option can select all pins to be used as segment drivers or all pins to be used as CMOS outputs.
I/O
PB0/AN0~ PB7/AN7
I/O
Pull-high
PC0/TMR2 PC1~PC5 PC6/TX PC7/RX PD0/PWM0 PD1/PWM1 PD2/PWM2 PD3/PWM3 PD4/INT0 PD5/INT1 PD6/TMR0 PD7/TMR1
I/O
Pull-high
I/O
Pull-high PWM Interrupt
OSC1 OSC2
I O
Crystal or RC
OSC3 OSC4 VLCD VMAX V1, V2, C1, C2 SEG0~SEG7
I O 3/4 3/4 I O
RTC or System Clock 3/4 3/4 3/4 SEG0~SEG7 or CMOS output
SEG8~SEG15
O
LCD driver outputs for LCD panel segments. A configuration option can SEG8~SEG15 or select all pins to be used as segment drivers or all pins to be used as CMOS output CMOS outputs. SEG16~SEG23 CMOS output 3/4 LCD driver outputs for LCD panel segments. Configuration options can select each pin to be used as either a segment driver or each pin to be used as a CMOS output. LCD driver outputs for LCD panel segments
SEG16~SEG23 SEG24~SEG45 COM0~COM2 COM3/SEG46
O O O
An LCD duty-cycle configuration option determines if SEG46 is config1/3 or 1/4 Duty ured as a segment driver or as a common output driver for the LCD COM3 or SEG46 panel. COM0~COM2 are the LCD common outputs.
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Pin Name VREF RES VDD VSS AVDD AVSS Note: I/O I I 3/4 3/4 I I Configuration Option
3/4
Description Reference voltage input pin. Schmitt Trigger reset input. Active low. Positive power supply Negative power supply, ground Positive analog power supply Negative analog power supply, ground
3/4 3/4 3/4
3/4 3/4
Each pin on Port A can be programmed through a configuration option to have a wake-up function. Individual pins can be selected to have a pull-high resistor. Pins V2, C1, C2 and segment pin SEG34 are not available on the 52-pin QFP package. Pins PB4/AN4~PB7/AN7 only exist on the 100-pin QFP package. Pins PC0~PC5 only exist on the 100-pin QFP package. Pin PD3/PWM3 only exists on the 100-pin QFP package. Pins PD7/TMR1 and PC0/TMR2 only exist on the 100-pin QFP package. The 56-pin SSOP and 52-pin QFP packages have only one external timer input TMR0. Segment pins SEG0~SEG15 and SEG35~SEG45 only exist on the 100-pin QFP package. For the 52-pin QFP and 56-pin SSOP, the VREF, AVDD are bonded together with VDD pin. For the 52-pin QFP and 56-pin SSOP, the AVSS is bonded together with VSS pin.
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V Input Voltage..............................VSS-0.3V to VDD+0.3V Storage Temperature ............................-50C to 125C Operating Temperature...........................-40C to 85C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol Parameter Test Conditions VDD 3/4 3/4 3/4 3V 5V 3V 5V 3V 5V 5V Conditions fSYS=4MHz fSYS=8MHz VREF=AVDD No load, fSYS=4MHz, ADC Off, UART Off No load, fSYS=4MHz, ADC Off, UART On (see Note 2) No load, fSYS=4MHz, ADC Off, UART On (see Note 3) No load, fSYS=8MHz, ADC Off, UART Off No load, fSYS=8MHz, ADC Off, UART On (see Note 2) Min. 2.2 3.3 3.0 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Typ. 3/4 3/4 3/4 1 3 2 4 1.5 3 4 Max. 5.5 5.5 5.5 2 5 4 8 3 6 8
Ta=25C Unit V V V mA mA mA mA mA mA mA
VDD AVDD IDD1
Operating Voltage Analog Operating Voltage (see Note 5) Operating Current (Crystal OSC, RC OSC) Operating Current (Crystal OSC, RC OSC) Operating Current (Crystal OSC, RC OSC) Operating Current (Crystal OSC, RC OSC) Operating Current (Crystal OSC, RC OSC)
IDD2
IDD3
IDD4
IDD5
5V
6
12
mA
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Symbol Parameter Operating Current (Crystal OSC, RC OSC) Operating Current (fSYS=32768Hz) Standby Current (*fS=T1) Standby Current (*fS=RTC OSC) Standby Current (*fS=WDT OSC) Test Conditions VDD 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V Conditions No load, fSYS=8MHz, ADC Off, UART On (see Note 3) No load, ADC Off, UART Off No load, system HALT, LCD Off at HALT, UART Off No load, system HALT, LCD On at HALT, C type, UART Off No load, system HALT, LCD On at HALT, C type, UART Off No load, system HALT, LCD On at HALT, R type, 1/2 bias, VLCD=VDD, UART Off (Low bias current option) No load, system HALT, LCD On at HALT, R type, 1/3 bias, VLCD=VDD, UART Off (Low bias current option) No load, system HALT, LCD On at HALT, R type, 1/2 bias, VLCD=VDD, UART Off (Low bias current option) No load, system HALT, LCD On at HALT, R type, 1/3 bias, VLCD=VDD, UART Off (Low bias current option) 3/4 3/4 3/4 3/4 3/4 3/4 52QFP, 56SSOP 100QFP AVDD=3V AVDD=5V VOL=0.1VDD Min. Typ. Max. Unit
IDD6
3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0 0.7VDD 0 0.9VDD 2.7 3.0 0 0 1.3 1.5 6 10 -2 -5
5 0.3 0.6 3/4 3/4 2.5 10 2 6 17 34 13 28 14 26 10 19 3/4 3/4 3/4 3/4 3.0 3.3 3/4 3/4 3/4 3/4 12 25 -4 -8
10 0.6 1 1 2 5 20 5 10 30 60 25 50 25 50 20 40 0.3VDD VDD 0.4VDD VDD 3.3 3.6 AVDD VREF AVDD AVDD 3/4 3/4 3/4 3/4
mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA V V V V V V V V V V mA mA mA mA
IDD7
ISTB1
ISTB2
ISTB3
ISTB4
Standby Current (*fS=RTC OSC)
ISTB5
Standby Current (*fS=RTC OSC)
3V 5V
ISTB6
Standby Current (*fS=WDT OSC)
3V 5V
ISTB7
Standby Current (*fS=WDT OSC)
3V 5V
VIL1 VIH1 VIL2 VIH2 VLVR VLVD VAD
Input Low Voltage for I/O Ports, TMR0, TMR1, INT0 and INT1 Input High Voltage for I/O Ports, TMR0, TMR1, INT0 and INT1 Input Low Voltage (RES) Input High Voltage (RES) Low Voltage Reset Voltage Low Voltage Detector Voltage A/D Input Voltage ADC Input Reference Voltage Range I/O Port Segment Logic Output Sink Current I/O Port Segment Logic Output Source Current
3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3V 5V 3V 5V
VREF
IOL1
IOH1
VOH=0.9VDD
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HT46RU66/HT46CU66
Symbol Parameter LCD Common and Segment Current LCD Common and Segment Current Test Conditions VDD 3V 5V 3V 5V Conditions VOL=0.1VDD Min. 210 350 -80 -180 3/4 3/4 No load, tAD=1ms AVDD=5V, VREF=AVDD, tAD=1ms AVDD=5V, VREF=AVDD, tAD=1ms 3/4 20 10 3/4 3/4 3/4 3/4 3/4 Typ. 420 700 -160 -360 60 30 0.5 1.5 3/4 2.5 3/4 Max. 3/4 3/4 3/4 3/4 100 50 1 3 2 4 12 Unit mA mA mA mA kW kW mA mA LSB LSB Bits
IOL2
IOH2
VOH=0.9VDD
RPH
Pull-high Resistance of I/O Ports 3V and INT0, INT1 5V Additional Power Consumption if A/D Converter is Used ADC Differential Non-Linear ADC Integral Non-Linear 3/4 3/4 3/4 3/4
IADC DNL INL
RESOLU Resolution Note:
1. *fS refer to the WDT clock option 2. UART On: UARTEN=1, TXEN=1, RXEN=1, BRGH=1, BRG=0 3. UART On: UARTEN=1, TXEN=0, RXEN=0, BRGH=1, BRG=0 4. ISTB1=WDT disable, ISTB2~ISTB7=WDT enable 5. Voltage level of AVDD and VDD must be the same. Ta=25C Test Conditions Min. VDD Conditions 2.2V~5.5V 3.3V~5.5V 2.2V~5.5V 3/4 2.2V~5.5V 3.3V~5.5V 3/4 3/4 3/4 Power-up or wake-up from HALT 3/4 3/4 3/4 3/4 400 400 3/4 3/4 0 0 45 32 1 3/4 1 1 3/4 3/4 3/4 3/4 32768 32768 3/4 3/4 90 65 3/4 1024 3/4 3/4 80 32 4000 8000 3/4 3/4 4000 8000 180 130 3/4 3/4 3/4 3/4 3/4 3/4 kHz kHz Hz Hz kHz kHz ms ms ms tSYS ms ms tAD tAD 3/4 3/4 3/4 3/4 3/4 3/4 3V 5V Typ. Max. Unit
A.C. Characteristics
Symbol Parameter System Clock (Crystal OSC, RC OSC) System Clock (32768Hz Crystal OSC) RTC Frequency Timer I/P Frequency (TMR0/TMR1)
fSYS1
fSYS2 fRTCOSC fTIMER
tWDTOSC Watchdog Oscillator Period tRES tSST tINT tAD tADC tADCS Note: External Reset Low Pulse Width System Start-up Timer Period Interrupt Pulse Width A/D Clock Period A/D Conversion Time A/D Sampling Time tSYS= 1/fSYS1 or 1/fSYS2
3/4 3/4 3/4 3/4 3/4 3/4
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Functional Description
Execution Flow The system clock is derived from either a crystal or an RC oscillator or a 32768Hz crystal oscillator. It is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. The pipelining scheme allows each instruction to be effectively executed in a cycle. If an instruction changes the value of the program counter, two cycles are required to complete the instruction.
T1 T2 T3 T4 T1 T2
Program Counter - PC The program counter is 14 bits wide and controls the sequence in which the instructions stored in the program ROM are executed. The contents of the PC can specify a maximum of 1638416 addresses. After accessing a program memory word to fetch an instruction code, the value of the PC is incremented by 1. The PC then points to the memory word containing the next instruction code. When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction,a subroutine call, interrupt or reset, etc., the
T3 T4 T1 T2 T3 T4
S y s te m O S C 2 (R C
C lo c k o n ly ) PC
PC
PC+1
PC+2
F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 )
Execution Flow Program Counter *13 0 0 0 0 0 0 0 *12 0 0 0 0 0 0 0 *11 0 0 0 0 0 0 0 *10 0 0 0 0 0 0 0 *9 0 0 0 0 0 0 0 *8 0 0 0 0 0 0 0 *7 0 0 0 0 0 0 0 *6 0 0 0 0 0 0 0 *5 0 0 0 0 0 0 0 *4 0 0 0 0 1 1 1 *3 0 0 1 1 0 0 1 *2 0 1 0 1 0 1 0 *1 0 0 0 0 0 0 0 *0 0 0 0 0 0 0 0
Mode Initial Reset External Interrupt 0 External Interrupt 1 Timer/Event Counter 0 Overflow Timer/Event Counter 1 Overflow UART Bus Interrupt Multi-function Interrupt Skip Loading PCL Jump, Call Branch Return from Subroutine
Program Counter + 2 (Within the current bank) *13 *12 *11 *10 *9 #9 S9 *8 #8 S8 @7 @6 @5 @4 @3 @2 @1 @0 #7 S7 #6 S6 #5 S5 #4 S4 #3 S3 #2 S2 #1 S1 #0 S0
BP.5 #12 #11 #10 S13 S12 S11 S10
Program Counter Note: *13~*0: Program counter bits #12~#0: Instruction code bits
1312 87 P ro g ra m
BP .5
S13~S0: Stack register bits @7~@0: PCL bits
0
C o u n te r
B a n k P o in te r (B P )
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HT46RU66/HT46CU66
microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writable register. By transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. As the Program Memory is stored in two Banks, the Bank selection is under the control of bit 5 of the Bank Pointer. It is this Bank Pointer bit that controls the highest address bit of the Program Counter as shown in the diagram. Program Memory The program memory is used to store the program instructions, which are to be executed. It also contains data, table, and interrupt entries, and is organized into a format of 1638416 bits, which are addressed by the PC and table pointer. The Program Memory is divided into two banks, Bank0 and Bank1. Each bank has a capacity of 819216 bits and is selected using bit BP.5 in the the bank pointer register. With BP = 000XXXXXB, Bank0 is selected and with BP = 001XXXXXB, Bank1 is selected. The JMP and CALL instructions provide only 13 bits of address to allow branching within any 8K program memory bank. When executing a JMP or CALL instruction, the user must ensure that the bank pointer bit, BP.5, is programmed so that the desired program memory bank is addressed. If a return from a CALL instruction or interrupt is executed, the entire 14 bit PC is popped off the stack. Therefore, manipulation of the BP.5 is not required when the RET or RETI instructions are executed. Certain locations in the Program Memory are reserved for special usage:
* Location 000H
000H 004H 008H 00CH 010H 014H 018H D e v ic e in itia liz a tio n p r o g r a m E x te r n a l in te r r u p t 0 s u b r o u tin e E x te r n a l in te r r u p t 1 s u b r o u tin e T im e r /e v e n t c o u n te r 0 in te r r u p t s u b r o u tin e T im e r /e v e n t c o u n te r 1 in te r r u p t s u b r o u tin e U A R T B u s In te rru p t M u lti- F u n c tio n In te r r u p t P ro g ra m M e m o ry (8 1 9 2
2 B ank)
n00H nFFH
L o o k - u p ta b le ( 2 5 6 w o r d s )
1F00H 1FFFH
L o o k - u p ta b le ( 2 5 6 w o r d s ) N o te : n ra n g e s fro m 1 6 b its 0 to 1 F
Program Memory
* Location 004H
Location 004H is reserved for the external interrupt service program. If the INT0 input pin is activated, the interrupt is enabled, and the stack is not full, the program begins execution at location 004H.
* Location 008H
Location 008H is also reserved for the external interrupt service program. If the INT1 input pin is activated, the interrupt is enabled, and the stack is not full, the program will jump to this location and begin execution.
* Location 00CH
Location 00CH is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results from a Timer/Event Counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program will jump to this location and begin execution.
* Location 010H
Location 010H is reserved for the Timer/Event Counter 1 interrupt service program. If a timer interrupt results from a Timer/Event Counter 1 overflow, and if the interrupt is enabled and the stack is not full, the program will jump to this location and begin execution.
* Location 014H
Location 000H is reserved for program initialisation. After a device reset, the program will jump to this location and begin execution.
Location 014H is reserved for the UART Bus interrupt service program. If the UART Bus interrupt resulting from a transmission flag or reception is completed, and if the interrupt is enabled and the stack is not full, the program will jump to this location and begin execution.
Instruction(s) TABRDC [m] TABRDL [m]
Table Location **13~*8 TBHP 111111 *7 @7 @7 *6 @6 @6 *5 @5 @5 *4 @4 @4 *3 @3 @3 *2 @2 @2 *1 @1 @1 *0 @0 @0
Table Location Note: *13~*0: Table location bits @7~@0: Table pointer lower-order bits (TBLP) 9 TBHP: Table pointer higher-order bits
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HT46RU66/HT46CU66
* Location 018H
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 3FH 40H TM R2 TM R2C M F IC USR UCR1 UCR2 T X R /R X R BRG ADRL ADRH ADCR ACSR In d ir e c t A d d r e s s in g R e g is te r 0 MP0 In d ir e c t A d d r e s s in g R e g is te r 1 MP1 BP ACC PCL TBLP TBLH RTCC STATUS IN T C 0 TM R0H TM R0L TM R0C TM R1H TM R1L TM R1C PA PAC PB PBC PC PCC PD PDC PW M0 PW M1 PW M2 PW M3 IN T C 1 TBHP S p e c ia l P u r p o s e D a ta M e m o ry
This area is reserved for the Multi-function interrupt service program. If a timer interrupt results from a Timer/Event Counter 2 overflow, or the real time clock time out, or Time base time out, and if the interrupt is enabled and the stack is not full, the program will jump to this location and begin execution.
* Table location
Any location in the Program Memory can be used as a look-up table. The instructions TABRDC [m] (page specified by the TBHP) for the current page, 1 page=256 words) and TABRDL [m] (the last page), transfer the contents of the lower-order byte to the specified data memory, and the contents of the higher-order byte to the TBLH register. This is the Table Higher-order byte register (08H). Only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are all transferred to the lower portion of the TBLH. The TBLH is read only, the higher-order byte table pointer TBHP (1FH) and the table pointer, TBLP, is a read/write register (07H), indicating the table location. Before accessing the table, the location should be placed in the TBHP and TBLP registers. All the table related instructions require 2 cycles to complete the operation. These areas may function as a normal Program Memory depending upon the users requirements. Stack Register - STACK The stack register is a special part of the memory used to save the contents of the program counter. The stack is organized into 16 levels and is neither part of the data nor part of the program, and is neither readable nor writeable. Its activated level is indexed by a stack pointer, known as SP, which is neither readable nor writeable. At the start of a subroutine call or an interrupt acknowledgment, the contents of the program counter is pushed onto the stack. At the end of the subroutine or interrupt routine, signaled by a return instruction, RET or RETI, the contents of the program counter is restored to its previous value from the stack. After a device reset, the stack pointer will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag is recorded but the acknowledge signal is still inhibited. Once the SP is decremented, using an RET or RETI instruction, the interrupt is serviced. This feature prevents stack overflow, allowing the programmer to use the structure easily. Likewise, if the stack is full, and a CALL is subsequently executed, a stack overflow occurs and the first entry is lost as only the most recent 16 return addresses are stored. Data Memory - RAM The Data Memory, RAM, has a structure of 6208 bits, and is divided into two functional groups, namely; special function registers, 448 bits, and general purpose data memory (Bank 0: 1928 bits, Bank 2: 1928 bits Rev. 1.00 10
FFH
G e n e ra D a ta 192 B (3 B a n k s : B a n k
lP Me y te 0,
u rp o s e m o ry s3 B ank2,B ank3)
:U nused R e a d a s "0 0 "
RAM Mapping July 10, 2006
HT46RU66/HT46CU66
and Bank 3: 1928 bits). Most of these registers are readable and writeable, although some are read only. The special function registers are overlapped in any bank. Of the two types of functional groups, the special function registers consist of an Indirect addressing register 0 (00H), a Memory pointer register 0 (MP0;01H), an Indirect addressing register 1 (02H), a Memory pointer register 1 (MP1;03H), a Bank pointer (BP;04H), an Accumulator (ACC;05H), a Program counter lower-order byte register (PCL;06H), a table pointer lower-order byte (TBLP;07H), a table pointer higher-order byte (TBHP;1FH), a Table higher-order byte register (TBLH;08H), a Real time clock control register (RTCC;09H), a Status register (STATUS;0AH), an Interrupt control register 0 (INTC0;0BH), a Timer/Event Counter 0 (TMR0H;0CH; TMR0L;0DH), a Timer/Event Counter 0 control register (TMR0C;0EH), a Timer/Event Counter 1 (TMR1H:0FH;TMR1L;10H), a Timer/Event Counter 1 control register (TMR1C;11H), a Timer/Event Counter 2 (TMR2;2DH), a Timer/Event Counter 2 control register (TMR2C;2EH), Interrupt control register 1 (INTC1;1EH), Multi-function Interrupt control register 1 (MFIC;2FH), PWM data register (PWM0;1AH, PWM1;1BH, PWM2;1CH, PWM3;1DH), the A/D result lower-order byte register (ADRL;24H), the A/D result higher-order byte register (ADRH;25H), the A/D control register (ADCR;26H), the A/D clock setting register (ACSR;27H), I/O registers (PA;12H, PB;14H, PC;16H, PD;18H) and I/O control registers (PAC;13H, PBC;15H, PCC;17H, PDC;19H), the UART Bus status register control register (USR;30H), the UART Bus control register 1 (UCR1;31H), the UART Bus control register 2 (UCR2;32H), the UART Bus transmit and receive register (TXR/RXR;33H), the UART Bus Baud Rate Generator register (BRG;34H). The Data Memory space before address 40H is reserved for future expansion usage and reading these locations will retrieve a value of 00H. The space before 40H overlaps in each bank. The general purpose data memory, addressed from 40H to FFH (Bank0; BP=0, Bank2; BP=2 or Bank3; BP=3), is used for data and control information under instruction commands. All of the data memory areas can directly handle arithmetic, logic, increment, decrement and rotate operations . Except for some dedicated bits, each bit in the data memory can be set and reset by SET [m].i and CLR [m].i. They are also indirectly accessible through the memory pointer registers, MP0;01H and MP1;03H. Indirect Addressing Register Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] and [02H] accesses the Data Memory pointed to by MP0 and MP1 respectively. Reading location 00H or 02H indirectly returns the result 00H. Writing to it indirectly results to no operation. The function of data movement between two indirect addressing registers is not supported. The memory pointer registers, MP0 and MP1, are both 8-bit registers used to access the Data Memory in combination with their corresponding indirect addressing registers. MP0 can only be used to access data from Bank 0, while MP1 can be used to access data from all banks. Accumulator - ACC The accumulator, ACC, is related to the ALU operations. It is also mapped to location 05H of the Data Memory, and is capable of operating with immediate data. The data movement between two data memory locations must pass through the ACC. Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operations and provides the following functions:
* Arithmetic operations (ADD, ADC, SUB, SBC, DAA) * Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment and Decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ, etc.)
The ALU not only saves the results of a data operation but also changes the status register. Status Register - STATUS The status register (0AH) is 8 bits wide and contains, a carry flag (C), an auxiliary carry flag (AC), a zero flag (Z), an overflow flag (OV), a power down flag (PDF), and a watchdog time-out flag (TO). It also records the status information and controls the operational sequence. Except for the TO and PDF flags, bits in the status register can be altered by instructions similar to the other registers. Data written into the status register does not alter the TO or PDF flags. Operations related to the status register, however, may yield different results from those intended. The TO and PDF flags can only be changed by a Watchdog Timer overflow, device power-up, or clearing the Watchdog Timer and executing the HALT instruction. The Z, OV, AC, and C flags reflect the status of the latest operations. On entering the interrupt sequence or executing a subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status is important, and if the subroutine is likely to corrupt the status register, the programmer should take precautions to save it properly.
Rev. 1.00
11
July 10, 2006
HT46RU66/HT46CU66
Bit No. 0 Label C Function C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation, otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction, otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is zero, otherwise Z is cleared. OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa, otherwise OV is cleared. PDF is cleared by either a system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction. TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0 Status (0AH) Register Interrupts - INTC0, INTC1, MFIC The device provides two external interrupts, two Internal Timer/Event Counter (0/1) interrupts, a UART Bus interrupt, and a Multi-function interrupt. The Multi-function interrupt includes the internal Timer/Event Counter 2 interrupt, the internal real time clock interrupt, and the internal time base interrupt . The Interrupt Control register 0, INTC0;0BH, interrupt control register 1, INTC1;1EH, and the Multi-Function interrupt control register, MFIC;2FH, contain the interrupt control bits that are used to set the enable/disable status and interrupt request flags. Once an interrupt subroutine is serviced, other interrupts are all blocked automatically as the EMI bit is cleared. This scheme may prevent any further interrupt nesting. Other interrupt requests may take place during this interval, but only the interrupt request flag will be recorded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bits in the INTC0, INTC1 and MFIC registers may be set in order to allow interrupt nesting. Once the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack should be prevented from becoming full. All these interrupts can support a wake-up function. As an interrupt is serviced, a control transfer occurs by pushing the contents of the program counter onto the stack followed by a branch to a subroutine at the specified location in the Program Memory. Only the contents of the program counter is pushed onto the stack. If the contents of the register or the status register is altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. External interrupts are triggered by an edge transition on pins INT0 or INT1 . A configuration option exists to select one of three transition types, either high to low, low to high or both. The related interrupt request flag, EIF0; bit 4 of the INTC0 register and EIF1; bit 5 of the INTC0 register, will be set when an external interrupt occurs. After the interrupt is enabled, the stack is not full, and the external interrupt is active, a subroutine call to location 04H or 08H occurs. The interrupt request flag, EIF0 or EIF1 and the EMI bits are all cleared to disable other maskable interrupts. The internal Timer/Event Counter 0 interrupt is initialised by setting the Timer/Event Counter 0 interrupt request flag, T0F; bit 6 of the INTC0 register, which is normally caused by a timer overflow. After the interrupt is enabled, and the stack is not full, and the T0F bit is set, a subroutine call to location 0CH occurs. The related interrupt request flag, T0F, is reset, and the EMI bit is cleared to disable other maskable interrupts. The Timer/Event Counter 1 and Timer/Event Counter 2 operates in the same manner, The Timer/Event Counter 1 related interrupt request flag is T1F, bit 4 of the INTC1 register, and its subroutine call location is 010H. The Timer/Event Counter 2 related interrupt request flags are MFF, bit 6 of the INTC1 register, and T2F, bit 4 of the MFIC register, and its subroutine call location is 018H. The related interrupt request flags, T1F and MFF, will be reset and the EMI bit cleared to disable further interrupts. T2F, bit 4 of the MFIC register, will not be cleared automatically, and should be cleared by the user. The UART Bus interrupt is initialized by setting the UART Bus interrupt request flag, URIF; bit 5 of the INTC1 register, caused by a Transmit enable, TXIF, or when one byte of data has been received, RXIF, or a transmit Idle, TIDF, is set or when the receive idle, RIDF, is set. When the interrupt is enabled, the stack is not full and the TXIF, RXIF, TIDF or RIDF bit is set, a subroutine call to location 014H will occur. The related interrupt request flag, URIF, will be reset and the EMI bit cleared to disable further interrupts. 12 July 10, 2006
1 2 3 4 5 6, 7
AC Z OV PDF TO 3/4
Rev. 1.00
HT46RU66/HT46CU66
The Multi-Function Interrupt, MFI, is initialised by setting the interrupt request flag, MFF; bit 6 of the INTC1 register, that is caused by a Timer 2 overflow, T2F; bit 4 of the MFIC register, caused by a regular real time clock time-out, RTF; bit 6 of the MFIC register or caused by a time base time-out, TBF; bit5 of the MFIC register. After the interrupt is enabled, EMFI=1, the stack is not full, and the MFF bit is set, a subroutine call to location 018H will occur. The related interrupt request flag, MFF, is reset and the EMI bit is cleared to disable further maskable interrupts. T2F, TBF and RTF indicate that a related interrupt has occurred. As these flags will not be cleared automatically after reading, they should be cleared by the user. During the execution of an interrupt subroutine, other maskable interrupt acknowledgments are all held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set both to 1, if the stack is not full. To return from the interrupt subroutine, a RET or RETI instruction may be executed. RETI sets the EMI bit and enables an interrupt service, but RET does not. Interrupts occurring in the interval between the rising edges of two consecutive T2 pulses are serviced on the latter of the two T2 pulses if the corresponding interrupts are enabled. In the case of simultaneous requests, the priorities in the following table apply. These can be masked by resetting the EMI bit. Function Controls the master (global) interrupt (1=enable; 0= disable) Controls the external interrupt 0 (1=enable; 0=disable) Controls the external interrupt 1 (1=enable; 0=disable) Controls the Timer/Event Counter 0 interrupt (1=enable; 0=disable) External interrupt 0 request flag (1=active; 0=inactive) External interrupt 1 request flag (1=active; 0=inactive) Internal Timer/Event Counter 0 request flag (1=active; 0=inactive) For test mode used only. Must be written as 0; otherwise may result in unpredictable operation. INTC0 (0BH) Register Bit No. 0 1 2 3, 7 4 5 6 Label ET1I EURI EMFI 3/4 T1F URIF MFF Function Controls the Timer/Event Counter 1 interrupt (1=enable; 0=disable) Control the UART Bus interrupt (1=enable; 0=disable) Control the Multi-function interrupt (1=enable; 0=disable) Unused bit, read as 0 Internal Timer/Event Counter 1 request flag (1=active; 0=inactive) UART Bus request flag (1=active; 0=inactive) Multi-function interrupt request flag (1=active; 0=inactive) INTC1 (1EH) Register Bit No. 0 1 2 3, 7 4 5 6 Label ET2I ETBI ERTI 3/4 T2F TBF RTF Function Control the Timer/Event Counter 2 interrupt (1=enable; 0=disable) Control the time base interrupt (1=enable; 0=disable) Control the real time clock interrupt (1=enable; 0=disable) Unused bit, read as 0 Timer/Event Counter 2 interrupt request flag (1=active; 0=inactive) Time base interrupt request flag (1=active; 0=inactive) Real time clock interrupt request flag (1=active; 0=inactive) MFIC (2FH) Register
Bit No. 0 1 2 3 4 5 6 7
Label EMI EEI0 EEI1 ET0I EIF0 EIF1 T0F 3/4
Rev. 1.00
13
July 10, 2006
HT46RU66/HT46CU66
Interrupt Source External Interrupt 0 External Interrupt 1 Timer/Event Counter 0 Overflow Timer/Event Counter 1 Overflow UART Bus Interrupt Multi-function Interrupt (Timer/Event Counter 2 / Real time clock / Time base overflow) Priority 1 2 3 4 5 6 Vector 04H 08H 0CH 10H 14H 18H flag, RTF; bit 6 of the MFIC register, the time base interrupt flag, TBF; bit 5 of the MFIC register, indicate that a related interrupt has occurred. As these flags will not be cleared automatically, they should be cleared by the user. The enable control Timer 2 interrupt, ET2I, the enable time base interrupt, ETBI, the enable real time clock interrupt, ERTI, constitute the Interrupt Control Register 2, MFIC, which is located at 2FH in the Program Memory. It is recommended that a program does not use the CALL instruction within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and the interrupt enabling is not well controlled, the original control sequence may be damaged if a CALL is executed. Oscillator Configuration The device provides three oscillator circuits for system clocks. These are an RC oscillator, a crystal oscillator and a 32768Hz crystal oscillator, the choice of which is determined by a configuration option. The Power Down mode will stop the system oscillator, if it is an RC or crystal oscillator type and will ignore external signals in order to conserve power. If the 32768Hz crystal oscillator is selected as the system oscillator, it will continue to run in the Power Down mode, but the instruction execution will be stopped. Since the 32768Hz oscillator is also designed for timing purposes, the internal timing (RTC, time base, WDT) operation still runs even if the system enters the Power Down mode. Of the three oscillators, if the RC oscillator is used, an external resistor between OSC1 and VSS is required, whose range should be within 24kW to 1MW. The system clock frequency divided by 4, can be monitored on pin OSC2 if a pull-high resistor is added. This can be used to synchronise external logic. The RC oscillator provides the most cost effective solution. However, the frequency of the oscillation may vary with VDD, temperature, and the chip itself due to process variations. It is therefore, not suitable for timing sensitive operations where accurate an oscillator frequency is desired.
V OSC3 OSC1
DD
The Timer/Event Counter 0 interrupt request flag, T0F, the external interrupt 1 request flag, EIF1, the external interrupt 0 request flag, EIF0, the enable Timer/Event Counter0 interrupt bit, ET0I, the enable external interrupt 1 bit, EEI1, the enable external interrupt 0 bit, EEI0, and the enable master interrupt bit, EMI, make up the Interrupt Control register 0, INTC0, which is located at 0BH in the Program Memory. The multi-function interrupt request flag, MFF, the UART interrupt request flag, URIF, the Timer/Event Counter 1 interrupt request flag, T1F, the enable multi-function interrupt bit, EMFI, and the enable UART interrupt bit, EURI, and the enable Timer/Event Counter 1 interrupt bit, ET1I, constitute the Interrupt Control register 1, INTC1, which is located at 1EH in the Program Memory. The Time base interrupt request flag, TBF, the real time interrupt request flag, RTF, the Timer/Event Counter 2 interrupt request flag, T2F, the enable time base interrupt bit, ETBI, the enable real time interrupt bit, ERTI, and the enable Timer/Event counter 2 interrupt bit, ET2I, constitute the Multi-function Interrupt Control register, MFIC, which is located at 2FH in the Program Memory. The EMI, EEI0, EEI1, ET0I, ET1I, EURI and EMFI bits are used to control the enabling/disabling of interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request flags, EIF0, EIF1, T0F, T1F, URIF, MFF, are set, they will remain in the INTC0 and INTC1 registers until the interrupts are serviced or cleared by a software instruction. The Timer/Event Counter 2 overflow interrupt flag, T2F; bit 4 of the MFIC register, the real time clock interrupt
470pF OSC1
OSC4 3 2 7 6 8 H z C r y s ta l/R T C O s c illa to r
OSC2 C r y s ta l O s c illa to r
fS
YS
/4 RC
OSC2 O s c illa to r
System Oscillator Note: 32768Hz crystal enable condition: For WDT clock source or for system clock source. The external resistor and capacitor components connected to the 32768Hz crystal are not necessary to provide oscillation. For applications where precise RTC frequencies are essential, these components may be required to provide frequency compensation due to different crystal manufacturing tolerances.
Rev. 1.00
14
July 10, 2006
HT46RU66/HT46CU66
If the crystal oscillator is to be used, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for oscillation, no other external components are required. A resonator may be connected between OSC1 and OSC2 to replace the crystal and to get a frequency reference, but two external capacitors must be be connected between OSC1, OSC2 and ground. The other oscillator circuit is for the real time clock or RTC, which has a fixed frequency of 32.768kHz. A 32.768kHz crystal oscillator should be connected between OSC3 and OSC4 for its implementation. The RTC oscillator circuit has a quick start up function which can be activated by setting the QOSC bit, which is bit 4 of the RTCC register. It is recommended to turn this bit on at power on, and then turn it off after 2 seconds to conserve power. The WDT oscillator is a free running on-chip RC oscillator, which requires no external components. When the system enters the power down mode, the system clock will stop, but the WDT oscillator will continue to operate, with a period of approximately 65ms at 5V. The WDT oscillator can be disabled by a configuration option to conserve power. Watchdog Timer - WDT The WDT clock source can come from its own dedicated internal WDT oscillator, from the instruction clock (system clock/4), or from the real time clock oscillator (RTC oscillator). The timer is designed to prevent software malfunctions or sequences from jumping to unknown locations with unpredictable results. The WDT can be disabled by a configuration option. If the WDT is disabled, all executions related to the WDT result in no operation. The WDT clock source is divided by 212~215 , the actual value chosen by a configuration option, to get the WDT time-out period. For the WDT internal oscillator, the minimum WDT time-out period is about 300ms~600ms. This time-out period may vary with temperature, VDD and process variations. By using configuration options to set the WDT prescaler, longer time-out periods can be realised. If the WDT time-out is selected as 215, the maximum time-out period is divided by 215~216. This will give a time of about 2.1s~4.3s for the internal WDT oscillator. If the WDT oscillator is disabled, the WDT clock may still come from the instruction clock. The WDT will operate in the same manner except that in the Power Down mode, the WDT will stop counting and lose its protecting purpose. In this situation the system can only be restarted by external logic. If the device operates in a noisy environment, using the on-chip WDT internal oscillator is strongly recommended, since the Power Down mode will stop the system clock. A WDT overflow under normal operation initialises a device reset and sets the status bit TO. In the Power Down mode, the overflow initialises a warm reset, and only the program counter and stack pointer are reset to zero. To clear the WDT contents, three methods can be adopted. These are an external reset which is a low level to RES, a software instruction, and a HALT instruction. There are two types of software instructions; the single CLR WDT instruction and the instruction pair - CLR WDT1 and CLR WDT2. Of these two types of instruction, only one type of instruction can be active at a time depending on the options - CLR WDT times selection option. If the CLR WDT is selected, i.e., CLR WDT times equal one, any execution of the CLR WDT instruction clears the WDT. In the case that CLR WDT1 and CLR WDT2 are chosen, i.e., CLR WDT times equal two, these two instructions have to be executed to clear the WDT, otherwise, the WDT may reset the device due to a time-out. Multi-function Timer The device provides a multi-function timer for the WDT, time base and the RTC but with different time-out periods. The multi-function timer consists of an 8-stage divider and a 7-bit prescaler, with the clock source coming from the WDT OSC or RTC OSC or the instruction clock (i.e., system clock divided by 4). The multi-function timer also provides a selectable frequency signal (ranging from fS/22 to fS/28) for the LCD driver circuits, and a selectable frequency signal, ranging from fS/22 to fS/29, for the buzzer output, setup by configuration options. It is recommended to select a frequency as near to 4kHz as possible for the LCD driver circuits for clarity.
S y s te m RTC OSC W DT OSC
C lo c k /4 32768H z ROM Code O p tio n fS D iv id e r fS /2
8
W DT P r e s c a le r M a s k O p tio n W D T C le a r CK R T CK R T
12kH z
T im e fS /2 15~ fS /2 14~ fS /2 13~ fS /2 12~
ou fS fS fS fS
tR eset /2 16 /2 15 /2 14 /2 13
Watchdog Timer
Rev. 1.00
15
July 10, 2006
HT46RU66/HT46CU66
Time Base The time base offers a periodic time-out period to generate a regular internal interrupt. Its time-out period ranges from 212/fS to 215/fS selected by options. If a time base time-out occurs, the related interrupt request flags, TBF; bit 5 of the MFIC register, and MFF; bit 6 of the INTC1 register, will be set. If the interrupt is enabled, and the stack is not full, a subroutine call to location 18H occurs. The time base time-out signal can also be applied as a clock source for the Timer/Event Counter 1 to obtain longer time-out periods.
fs D iv id e r P r e s c a le r ROM Code O p tio n T im e B a s e In te r r u p t fS /2 12~ fS /2 15
Power Down Operation - HALT The Power Down mode is initialised by the HALT instruction and results in the following.
* The system oscillator turns off but the WDT oscillator
keeps running if the internal WDT oscillator or the real time clock is selected.
* The contents of the on-chip RAM and of the registers
remain unchanged.
* The WDT is cleared and starts recounting, if the WDT
clock source comes from the WDT oscillator or the real time clock oscillator.
* All I/O ports maintain their original status. * The PDF flag is set but the TO flag is cleared. * The LCD driver keeps running, if the WDT OSC or
ROM
C o d e O p tio n
RTC OSC is selected. The system leaves the Power Down mode by way of an external reset, an interrupt, an external falling edge signal on port A, or a WDT overflow. An external reset causes device initialisation, and a WDT overflow performs a warm reset. After examining the TO and PDF flags, the reason behind the chip reset can be determined. The PDF flag is cleared by a system power-up or by executing the CLR WDT instruction, and is set by executing the HALT instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, and leaves the other registers in their original state. A Port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in Port A can be independently selected to wake up the device via configuration options. Awakening from an I/O port stimulus, the program resumes execution of the next instruction. On the other hand, awakening from an interrupt, two sequence may occur. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program resumes execution at the next instruction. But if the interrupt is enabled, and the stack is not full, the regular interrupt response takes place. When an interrupt request flag is set before entering the HALT state, the system cannot be awakened using that interrupt. If wake-up events occur, it takes 1024 tSYS (system clock period) to resume normal operation. In other words, a dummy period is inserted after a wake-up. If a wake-up results from an interrupt acknowledge, the actual interrupt subroutine execution is delayed by more than one cycle. However, if a wake-up results in the next instruction execution, the execution will be performed immediately after the dummy period has finished. To minimize power consumption, all the I/O pins should be carefully managed before entering the Power Down state.
L C D D r iv e r ( fS /2 2 ~ fS /2 8 ) B u z z e r (fS /2 2~ fS /2 9)
Time Base Real Time Clock - RTC The real time clock operates in the same manner as the time base in that it is used to supply a regular internal interrupt. Its time-out period ranges from fS/28 to fS/215, the actual value of which is setup by software programming. Writing data to the RT2, RT1 and RT0 bits in the RTCC register, provides various time-out periods. If an RTC time-out occurs, the related interrupt request flag, RTF; bit 6 of the MFIC and MFF; bit 6 of the INTC1, is set. If the interrupt is enabled, and the stack is not full, a subroutine call to location 18H occurs. The real time clock time-out signal can also be applied as a clock source for Timer/Event Counter 0 in order to get longer time-out period.
fS D iv id e r RT2 RT1 RT0 P r e s c a le r
8 to 1 M U X
2 8/fS ~ 2 15/fS R T C In te rru p t
Real Time Clock
RT2 0 0 0 0 1 1 1 1
RT1 0 0 1 1 0 0 1 1
RT0 0 1 0 1 0 1 0 1
RTC Clock Divided Factor 2 8* 2 9* 210* 211* 212 213 214 215
Note: * not recommended to be used Rev. 1.00 16 July 10, 2006
HT46RU66/HT46CU66
Reset There are several ways in which a reset may occur.
* RES is reset during normal operation * Power on reset * RES is reset during a Power Down * WDT time-out is reset during normal operation * WDT time-out during a Power Down
The functional unit chip reset status is shown below. Program Counter Interrupt Prescaler, Divider WDT, RTC, Time Base Timer/event Counter 000H Disabled Cleared Cleared. After a master reset, the WDT starts counting Off Input mode Points to the top of the stack
A WDT time-out when the device is in the Power Down mode differs from the other reset conditions, as it performs a warm reset that resets only the program counter and SP and leaves the other circuits in their original state. Some registers remain unaffected during the other reset conditions. Most registers are reset to their initial condition once the reset conditions are met. By examining the PDF and TO flags, the program can distinguish between the different types of resets. TO 0 u 0 1 1 PDF 0 u 1 u 1 RESET Conditions RES reset during power-up RES reset during normal operation RES Wake-up HALT WDT time-out during normal operation WDT Wake-up HALT
Input/output Ports Stack Pointer
V
DD
0 .0 1 m F * 100kW RES 10kW 0 .1 m F *
Reset Circuit Note: * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference.
Note: u stands for unchanged To guarantee that the system oscillator has started and stabilized, the SST (System Start-up Timer) provides an extra delay of 1024 system clock pulses when the system awakens from the Power Down mode or during power up.
HALT
W DT
W DT T im e - o u t R eset E x te rn a l
W a rm
R eset
VDD RES S S T T im e - o u t C h ip R eset tS
ST
RES SST 1 0 - b it R ip p le C o u n te r P o w e r - o n D e te c tio n
OSC1
C o ld R eset
Reset Timing Chart Reset Configuration
Rev. 1.00
17
July 10, 2006
HT46RU66/HT46CU66
The register states are summarized below: Register MP0 MP1 BP ACC Program Counter TBLP TBLH RTCC STATUS INTC0 TMR0H TMR0L TMR0C TMR1H TMR1L TMR1C PA PAC PB PBC PC PCC PD PDC PWM0 PWM1 PWM2 PWM3 INTC1 TBHP ADRL ADRH ADCR ACSR TMR2 TMR2C MFIC USR Reset (Power On) xxxx xxxx xxxx xxxx 0000 0000 xxxx xxxx 0000H xxxx xxxx xxxx xxxx --00 0111 --00 xxxx 0000 0000 xxxx xxxx xxxx xxxx 00-0 1000 xxxx xxxx xxxx xxxx 0000 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx -000 -000 xxxx xxxx xxxx ---xxxx xxxx 0100 0000 1--- --00 xxxx xxxx 00-0 1000 -000 -000 0000 1011 WDT Time-out RES Reset (Normal Operation) (Normal Operation) uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu 0000H uuuu uuuu uuuu uuuu --00 0111 --1u uuuu 0000 0000 xxxx xxxx xxxx xxxx 00-0 1000 xxxx xxxx xxxx xxxx 0000 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx -000 -000 uuuu uuuu xxxx ---xxxx xxxx 0100 0000 1--- --00 xxxx xxxx 00-0 1000 -000 -000 0000 1011 uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu 0000H uuuu uuuu uuuu uuuu --00 0111 --uu uuuu 0000 0000 xxxx xxxx xxxx xxxx 00-0 1000 xxxx xxxx xxxx xxxx 0000 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx -000 -000 uuuu uuuu xxxx ---xxxx xxxx 0100 0000 1--- --00 xxxx xxxx 00-0 1000 -000 -000 0000 1011 RES Reset (HALT) uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu 0000H uuuu uuuu uuuu uuuu --00 0111 --01 uuuu 0000 0000 xxxx xxxx xxxx xxxx 00-0 1000 xxxx xxxx xxxx xxxx 0000 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx -000 -000 uuuu uuuu xxxx ---xxxx xxxx 0100 0000 ---- --00 xxxx xxxx 00-0 1000 -000 -000 0000 1011 WDT Time-out (HALT)* uuuu uuuu uuuu uuuu 00u0 00uu uuuu uuuu 0000H uuuu uuuu uuuu uuuu --uu uuuu --11 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uu-u uuuu uuuu uuuu uuuu uuuu uuuu u--uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu -uuu uuuu uuuu uuuu ---uuuu uuuu uuuu uuuu u--- --uu uuuu uuuu uu-u uuuu -uuu -uuu uuuu uuuu
Rev. 1.00
18
July 10, 2006
HT46RU66/HT46CU66
Register UCR1 UCR2 TXR/RXR BRG Note: Reset (Power On) 0000 00x0 0000 0000 xxxx xxxx xxxx xxxx * stands for warm reset u stands for unchanged x stands for unknown The event count mode is used to count external events, which means that the clock source comes from the external, TMR0, TMR1 or TMR2 pin. The timer mode functions as a normal timer with the clock source coming from the internally selected clock source. Finally, the pulse width measurement mode can be used to count the duration of a high or low level external signal on pin TMR0, TMR1 or TMR2. The counting is based on the internally selected clock source. In the event count or timer mode, the Timer/Event Counter 0 (1) starts counting at the current contents in the timer/event counter and ends at FFFFH. Timer/Event Counter 2 starts counting at the current contents in the timer/event counter and ends at FFH. Once an overflow occurs, the counter is reloaded from the timer/event counter preload register, and generates an interrupt request flag which are T0F; bit 6 of INTC0, T1F; bit 4 of INTC1, T2F; bit 4 of MFIC and bit 6 of INTC1. To enable the pulse width measurement mode, the operating mode select bits should both be set high. After the TMR0/TMR1/TMR2 pin has received a transient from low to high, or high to low if the T0E/T1E/T2E bit is 0, it will start counting until the TMR0/TMR1/ TMR2 pin returns to its original level a which point the T0ON/T1ON/T2ON bit will be auomatically reset. The measured result remains in the timer/event counter even if the activated transient occurs again. In other words, only a single shot measurement can be made. Not until the T0ON/T1ON/T2ON bit is again set by the program, can further pulse width measurements be made. In this operation mode, the timer/event counter begins counting not according to the logic level but to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter register and issues an interrupt request, as in the other two modes, i.e., event and timer modes. To enable the counting operation, the Timer ON bit, T0ON; bit 4 of TMR0C, T1ON; bit 4 of TMR1C, or T2ON; bit 4 of TMR2C, should be set to 1. In the pulse width measurement mode, the T0ON/T1ON/ T2ON is automatically cleared after a measurement cycle is comp l e t e d . B u t i n t h e o t h e r t w o m o d e s, t h e T0ON/T1ON/T2ON can only be reset by instructions. 19 July 10, 2006 WDT Time-out RES Reset (Normal Operation) (Normal Operation) 0000 00x0 0000 0000 xxxx xxxx xxxx xxxx 0000 00x0 0000 0000 xxxx xxxx xxxx xxxx RES Reset (HALT) 0000 00x0 0000 0000 xxxx xxxx xxxx xxxx WDT Time-out (HALT)* uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
Timer/Event Counter Three timer/event counters are implemented in this microcontroller. The Timer/Event Counter 0 contains a 16-bit programmable count-up counter whose clock may come from an external or internal source. Its internal clock source comes from fSYS. The Timer/Event Counter 1 contains a 16-bit programmable count-up counter whose clock may come from an external or internal source. Its internal clock source comes from either fSYS/4 or the 32768Hz RTC oscillator selected via configuration option. The Timer/Event Counter 2 contains an 8-bit programmable count-up counter whose clock may come from an external or internal source. Its internal clock source comes from fSYS. The external clock input allows the user to count external events, measure time intervals or pulse widths, or generate an accurate time base. There are eight registers related to the Timer/Event Counter 0; TMR0H (0CH), TMR0L (0DH), TMR0C (0EH) and the Timer/Event Counter 1; TMR1H (0FH), TMR1L (10H), TMR1C (11H) and the Timer/Event Counter 2; TMR2 (2CH) TMR2C (2DH). Writing to TMR0L (TMR1L) will only put the written data into an internal lower-order byte buffer (8-bit) while writing to TMR0H (TMR1H) will transfer the specified data and the contents of the lower-order byte buffer into the TMR0H (TMR1H) and TMR0L (TMR1L) registers, respectively. The Timer/Event Counter 1/0 preload register is changed by each write operation to TMR0H (TMR1H). Reading from the TMR0H (TMR1H) will latch the contents of the TMR0H (TMR1H) and TMR0L (TMR1L) counters to the destination and the lower-order byte buffer, respectively. Reading from TMR0L (TMR1L) will read the contents of the lower-order byte buffer. Writing to TMR2 places the start value into the Timer/Event Counter 2 preload register, and reading from TMR2 retrieves the contents of the Timer/Event Counter 2. The TMR0C (TMR1C,TMR2C) register is the Timer/Event Counter 0 (1, 2) control register, which defines the operating mode, enable or disable function and the active edge. The T0M0, T0M1 (TMR0C), T1M0, T1M1 (TMR1C) and T2M0, T2M1 (TMR2C) bits define the operational mode.
Rev. 1.00
HT46RU66/HT46CU66
The overflow of the Timer/Event Counter 0/1/2 is one of the wake-up sources. The Timer/Event Counter 0/1 can also be applied to a PFD or Programmable Frequency Divider whose output is on pin PA3 via a configuration option. Only one PFD (PFD0 or PFD1) can be applied to PA3 by options. No matter what the operation mode is, writing a 0 to ET0I, ET1I or ET2I disables the related interrupt service. When the PFD function is selected, executing the SET [PA].3 instruction will enable the PFD output and executing the CLR [PA].3 instruction will disable the PFD output. If the timer/event counter is not running, writing data to the timer/event counter preload register will also reload that data to the timer/event counter. But if the timer/event counter running, data written to the timer/event counter is kept only in the timer/event counter preload register. The timer/event counter continues to operate until an overflow occurs at which point the new data will be loaded from the preload register into the timer/event counter. When the timer/event counter is read, the clock is blocked to avoid errors. As this may results in a counting error, blocking of the clock should be taken into account by the programmer. It is strongly recommended to load a desired value into the TMR0/TMR1/TMR2 registers first, before turning on the related timer/event counter, for proper operation since the initial value of the TMR0/TMR1/TMR2 registers are unknown. Due to the timer/event counter scheme, the programmer should pay special attention to the instruction to enable then disable the timer for the first time, whenever there is a need to use the timer/event counter function, to avoid unpredictable result. After this procedure, the timer/event counter function can be operated normally. The bit0~bit2 of the TMR0C/TMR2C (T0PSC2~0/ T2PSC2~0) can be used to define the pre-scaling stages of the internal clock sources of the timer/event counter. The overflow signal of the timer/event counter can be used to generate the PFD signal. The timer prescaler is also used as the PWM counter.
PW M (6 + 2 ) o r (7 + 1 ) C o m p a re fS
YS
T o P D 0 /P D 1 /P D 2 /P D 3 C ir c u it
D a ta B u s L o w B y te B u ffe r
8 - s ta g e P r e s c a le r 8 -1 M U X T0PSC 2~T0PSC 0 TM R0 T0E T0M 1 T0M 0 T0O N P u ls e W id th M e a s u re m e n t M o d e C o n tro l f IN
T
T0M 1 T0M 0 1 6 - B it P r e lo a d R e g is te r R e lo a d
H ig h B y te
Low
B y te
O v e r flo w
to In te rru p t
1 6 - B it T im e r /E v e n t C o u n te r PFD0
Timer/Event Counter 0
D a ta B u s L o w B y te B u ffe r
T
32768H z
fS
YS
/4
MUX T1S TM R1
f IN
T1M 1 T1M 0 T1E 1 6 - B it P r e lo a d R e g is te r P u ls e W id th M e a s u re m e n t M o d e C o n tro l R e lo a d
T1M 1 T1M 0 T1O N
H ig h B y te
Low
B y te
O v e r flo w to In te r r u p t
1 6 - B it T im e r /E v e n t C o u n te r PFD1
Timer/Event Counter 1
Rev. 1.00
20
July 10, 2006
HT46RU66/HT46CU66
fS
YS
8 - s ta g e P r e s c a le r 8 -1 M U X T2PSC 2~T2PSC 0 (1 /1 ~ 1 /1 2 8 ) TM R2 T2E T2M 1 T2M 0 T2O N P u ls e W id th M e a s u re m e n t M o d e C o n tro l 8 - B it T im e r /E v e n t C o u n te r (T M R 2 ) O v e r flo w to In te rru p t f IN
T
D a ta B u s T2M 1 T2M 0 8 - B it T im e r /E v e n t C o u n te r P r e lo a d R e g is te r R e lo a d
Timer/Event Counter 2
PFD0 M PFD1
U X
T
Q
PFD
P A 3 D a ta C T R L P F D S o u rc e ( O p tio n )
PFD Source Option
Bit No.
Label
Function Defines the prescaler stages, T0PSC2, T0PSC1, T0PSC0= 000: fINT=fSYS 001: fINT=fSYS/2 010: fINT=fSYS/4 011: fINT=fSYS/8 100: fINT=fSYS/16 101: fINT=fSYS/32 110: fINT=fSYS/64 111: fINT=fSYS/128 Defines the TMR0 active edge of the timer/event counter: In Event Counter Mode (T0M1,T0M0)=(0,1): 1:count on falling edge; 0:count on rising edge In Pulse Width measurement mode (T0M1,T0M0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge Enables/disables the timer counting (0=disable; 1=enable) Unused bit, read as 0 Defines the operating mode, T0M1, T0M0: 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMR0C (0EH) Register
0 1 2
T0PSC0 T0PSC1 T0PSC2
3
T0E
4 5
T0ON 3/4
6 7
T0M0 T0M1
Rev. 1.00
21
July 10, 2006
HT46RU66/HT46CU66
Bit No. 0~2 Label 3/4 Unused bit, read as 0 Defines the TMR1 active edge of the timer/event counter: In Event Counter Mode (T1M1,T1M0)=(0,1): 1:count on falling edge; 0:count on rising edge In Pulse Width measurement mode (T1M1,T1M0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge Enables/disables the timer counting (0=disable; 1=enable) Defines the TMR1 internal clock source. (0=fSYS/4; 1=32768Hz) Defines the operating mode, T1M1, T1M0: 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMR1C (11H) Register Bit No. Label Function Defines the prescaler stages, T2PSC2, T2PSC1, T2PSC0= 000: fINT=fSYS 001: fINT=fSYS/2 010: fINT=fSYS/4 011: fINT=fSYS/8 100: fINT=fSYS/16 101: fINT=fSYS/32 110: fINT=fSYS/64 111: fINT=fSYS/128 Defines the TMR2 active edge of the timer/event counter: In Event Counter Mode (T2M1,T2M0)=(0,1): 1:count on falling edge; 0:count on rising edge In Pulse Width measurement mode (T2M1,T2M0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge Enables/disables the timer counting (0=disable; 1=enable) Unused bit, read as 0 Defines the operating mode, T2M1, T2M0: 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMR2C (2EH) Register Function
3
T1E
4 5
T1ON T1S
6 7
T1M0 T1M1
0 1 2
T2PSC0 T2PSC1 T2PSC2
3
T2E
4 5
T2ON 3/4
6 7
T2M0 T2M1
Rev. 1.00
22
July 10, 2006
HT46RU66/HT46CU66
Input/Output Ports There are 32 bidirectional input/output lines in the device, labeled as PA, PB, PC and PD, which are mapped to the data memory of [12H], [14H], [16H] and [18H] respectively. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction MOV A,[m] (m=12H, 14H, 16H or 18H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC, PBC, PCC, PDC) to control the input/output configuration. With this control register, a CMOS output or a Schmitt Trigger input with or without pull-high resistor structures can be reconfigured dynamically under software control. To function as an input, the corresponding latch of the control register must be setup as a 1. The input source also depends on the control register. If the control register bit is 1, the input will read the pad state. If the control register bit is 0, the contents of the latches will move to the internal bus. The latter is possible in the read-modify-write instruction. For an output function, CMOS is the only configuration. These control registers are mapped to locations 13H, 15H, 17H and 19H. After a device reset, these I/O lines will default to an input state and will be either high or floating, depending upon the pull-high configuration options. Each bit of these input/output latches can be set or cleared by the SET [m].i and CLR [m].i bit manipulation instructions. Some instructions first input data and then follow the output operations. For example, SET [m].i, CLR [m].i, CPL [m], CPLA [m] read the entire port states into the CPU, execute the defined bit operations, and then write the results back to the latches or the accumulator. Each line of port A has the capability of waking-up the device. Each I/O port has a pull-high option. Once the pull-high option is selected, the I/O port has a pull-high resistor, otherwise, theres none. Take note that a non-pull-high I/O port operating in input mode will cause a floating state. PA0, PA1, PA3, PD4, PD5, PD6 and PD7 are pin-shared with BZ, BZ, PFD, INT0, INT1, TMR0 and TMR1 pins respectively. The PC0, PC6 and PC7 pins are pin-shared with TMR2, TX and RX. PA0 and PA1 are pin-shared with the BZ and BZ signals, respectively. If the BZ/BZ option is selected, the output signal in output mode of PA0/PA1 will be the buzzer signal generated by the Multi-function timer. The input mode always remain in its original functions. Once the BZ/BZ option is selected, the buzzer output signals are controlled by the PA0 data register only. The I/O functions of PA0/PA1 are shown below.
PAC Register PAC0 0 0 0 0 1 1 Note:
PAC Register PAC1 0 0 1 1 0 1
PA Data Register PA0 1 0 1 0 x x
PA Data Register PA1 x x x x D x
Output Function PA0=BZ, PA1=BZ PA0=0, PA1=0 PA0=BZ, PA1=input PA0=0, PA1=input PA0=input, PA1=0 PA0=input, PA1=input
x stands for dont care D stands for Data 0 or 1
PA3 is pin-shared with the signal. If the PFD option is selected and if PA3 is setup as an output, then the output signal on the PA3 pin will be the PFD signal, generated by the timer/event counter overflow signal. If setup as an input it will function as a normal input pin. Once the PFD option is selected, the PFD output signal is controlled by the PA3 data register only. Writing a 1 to the PA3 data register will enable the PFD output function while writing a 0 will force the PA3 pin to remain at 0. The I/O functions of PA3 are shown below. I/O Mode PA3 Note: I/P (Normal) Logical Input O/P (Normal) Logical Output I/P (PFD) Logical Input O/P (PFD) PFD (Timer on)
The PFD frequency is the timer/event counter overflow frequency divided by 2.
Rev. 1.00
23
July 10, 2006
HT46RU66/HT46CU66
Port PB can also be used as A/D converter inputs. There is a PWM function shared with PD0/PD1/PD2/PD3. If the PWM function is enabled, the PWM0/PWM1/PWM2/ PWM3 signal will appear on PD0/PD1/PD2/PD3, if PD0/ PD1/ PD2/PD3 are operating in output mode. Writing 1 to the PD0~PD3 data register will enable the PWM output function while writing 0 will force the PD0~PD3 to remain at 0. The I/O functions of the PD0/PD1/PD2/PD3 are shown below. I/O Mode PD0~PD3 I/P (Normal) Logical Input O/P (Normal) Logical Output I/P (PWM) Logical Input O/P (PWM) PWM0~PWM3
It is recommended that unused or not bonded out I/O lines should be set as output pins by software instruction to avoid consuming power under input floating state. The definitions of the PFD control signal and PFD output frequency are listed in the following table. Timer OFF OFF ON ON Note: Timer Preload Value X X N N PA3 Data Register 0 1 0 1 PA3 Pad State 0 U 0 PFD PFD Frequency X X X fTMR/[2(M-N)]
X stands for unused U stands for unknown M is 65536 for PFD0 or PFD1 N is the preload value for the timer/event counter fTMR is input clock frequency for timer/event counter
V C o n tr o l B it D a ta B u s D CK Q S C h ip R e s e t R e a d C o n tr o l R e g is te r W r ite C o n tr o l R e g is te r Q P u ll- h ig h O p tio n
DD
D a ta B it Q D CK Q S M U X
W r ite D a ta R e g is te r
P A 0 /P A 1 /P A 3 /P D 0 /P D 1 /P D 2 /P D 3 B Z /B Z /P F D /P W M 0 /P W M 1 /P W M 2 /P W M 3 M U X R e a d D a ta R e g is te r S y s te m W a k e -u p ( P A o n ly ) IN IN TM TM T0 T1 R0 R1 fo fo fo fo rP rP rP rP D4 D5 D6 D7 on on on on ly ly ly ly
PA0 PA1 PA2 PA3 PA4 PB0 PC0 PC1 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7
/B Z /B Z /P F D ~PA7 /A N 0 ~ P B 7 /A N 7 /T M R 2 ~PC5 /P W M 0 /P W M 1 /P W M 2 /P W M 3 /IN T 0 /IN T 1 /T M R 0 /T M R 1
EN
W a k e - u p O p tio n s
Input/Output Ports
Rev. 1.00
24
July 10, 2006
HT46RU66/HT46CU66
V C o n tr o l B it D a ta B u s D CK S C h ip R e s e t P C 6 /T X R e a d C o n tr o l R e g is te r D a ta B it D W r ite D a ta R e g is te r CK Q S M F ro m UART TX M R e a d D a ta R e g is te r U X U X & TXEN Q Q W r ite C o n tr o l R e g is te r Q P u ll- h ig h O p tio n
DD
UARTEN
PC6/TX Input/Output Ports
V C o n tr o l B it D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r P C 7 /R X D a ta B it Q D CK S M U X R e a d D a ta R e g is te r To UART RX Q D CK S Q Q P u ll- h ig h O p tio n
DD
W r ite D a ta R e g is te r
PC7/RX Input/Output Ports
Pulse Width Modulator Each devices is provided with either three or four Pulse Width Modulation (PWM) outputs, depending upon which package type is selected. Useful for such applications such as motor speed control, the PWM function provides outputs with a fixed frequency but with a duty cycle that can be varied by setting particular values into the corresponding PWM register. A single register, located in the Data Memory is assigned to each PWM output. For devices with three PWM outputs, these registers are known as PWM0, PWM1 and PWM2. Devices with four PWM outputs require a further additional register known as PWM3. It is here that the 8-bit value, which represents the overall
duty cycle of one modulation cycle of the output waveform, should be placed. To increase the PWM modulation frequency, each modulation cycle is subdivided into two or four individual modulation subsections, known as the 7+1 mode or 6+2 mode respectively. The device can choose which mode to use by selecting the appropriate configuration option. When a mode configuration option is chosen, it applies to all PWM outputs on that device. Note that when using the PWM, it is only necessary to write the required value into the appropriate PWM register and select the required mode configuration option, the subdivision of the waveform into its sub-modulation cycles is done automatically within the microcontroller hardware.
Rev. 1.00
25
July 10, 2006
HT46RU66/HT46CU66
For all devices, the PWM clock source is the system clock fSYS. Package 52/56-pin 100-pin Channels 3 4 PWM Mode 6+2 or 7+1 6+2 or 7+1 Output Pin PD0/PD1/PD2 PD0/PD1/PD2/PD3 PWM Function Table This method of dividing the original modulation cycle into a further 2 or 4 sub-cycles enable the generation of higher PWM frequencies which allow a wider range of applications to be served. As long as the periods of the generated PWM pulses are less than the time constants of the load, the PWM output will be suitable as such long time constant loads will average out the pulses of the PWM output. The difference between what is known as the PWM cycle frequency and the PWM modulation frequency should be understood. As the PWM clock is the system clock, fSYS, and as the PWM value is 8-bits wide, the overall PWM cycle frequency is fSYS/256. However, when in the 7+1 mode of operation the PWM modulation frequency will be fSYS/128, while the PWM modulation frequency for the 6+2 mode of operation will be fSYS/64. PWM Modulation Frequency fSYS/64 for (6+2) bits mode fSYS/128 for (7+1) bits mode
* 6+2 PWM Mode
PWM Register Name PWM0/PWM1/PWM2 PWM0/PWM1/PWM2/PWM3
four individual sub-cycles known as modulation cycle 0 ~ modulation cycle 3, denoted as i in the table. Each one of these four sub-cycles contains 64 clock cycles. In this mode, a modulation frequency increase of four is achieved. The 8-bit PWM register value, which represents the overall duty cycle of the PWM waveform, is divided into two groups. The first group which consists of bit2~bit7 is denoted here as the DC value. The second group which consists of bit0~bit1 is known as the AC value. In the 6+2 PWM mode, the duty cycle value of each of the four modulation sub-cycles is shown in the following table. Parameter Modulation cycle i (i=0~3) AC (0~3) iPWM Cycle PWM Cycle Frequency Duty fSYS/256 [PWM]/256
6+2 Mode Modulation Cycle Values The following diagram illustrates the waveforms associated with the 6+2 mode PWM operation. It is important to note how the single PWM cycle is subdivided into 4 individual modulation cycles, numbered from 0~3 and how the AC value is related to the PWM value.
Each full PWM cycle, as it is controlled by an 8-bit PWM register, has 256 clock periods. However, in the 6+2 PWM mode, each PWM cycle is subdivided into
fS
YS
/2
[P W M ] = 1 0 0 PW M [P W M ] = 1 0 1 PW M [P W M ] = 1 0 2 PW M [P W M ] = 1 0 3 PW M PW M 2 6 /6 4 m o d u la tio n p e r io d : 6 4 /fS M o d u la tio n c y c le 0
YS
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4 M o d u la tio n c y c le 1 PW M
2 6 /6 4 M o d u la tio n c y c le 2 c y c le : 2 5 6 /fS
YS
2 5 /6 4 M o d u la tio n c y c le 3
2 6 /6 4 M o d u la tio n c y c le 0
6+2 PWM Mode
b7 b0 PW M AC R e g is te r v a lu e (6 + 2 ) M o d e
D C v a lu e
PWM Register for 6+2 Mode Rev. 1.00 26 July 10, 2006
HT46RU66/HT46CU66
* 7+1 PWM Mode
Parameter Modulation cycle i (i=0~1)
AC (0~1) iEach full PWM cycle, as it is controlled by an 8-bit PWM register, has 256 clock periods. However, in the 7+1 PWM mode, each PWM cycle is subdivided into two individual sub-cycles known as modulation cycle 0 ~ modulation cycle 1, denoted as i in the table. Each one of these two sub-cycles contains 128 clock cycles. In this mode, a modulation frequency increase of two is achieved. The 8-bit PWM register value, which represents the overall duty cycle of the PWM waveform, is divided into two groups. The first group which consists of bit1~bit7 is denoted here as the DC value. The second group which consists of bit0 is known as the AC value. In the 7+1 PWM mode, the duty cycle value of each of the two modulation sub-cycles is shown in the following table.
fS
YS
Duty Cycle DC + 1 128 DC 128
7+1 Mode Modulation Cycle Values The following diagram illustrates the waveforms associated with the 7+1 mode PWM operation. It is important to note how the single PWM cycle is subdivided into 2 individual modulation cycles, numbered 0 and 1 and how the AC value is related to the PWM value.
/2
[P W M ] = 1 0 0 PW M [P W M ] = 1 0 1 PW M [P W M ] = 1 0 2 PW M [P W M ] = 1 0 3 PW M 5 2 /1 2 8 PW M m o d u la tio n p e r io d : 1 2 8 /fS M o d u la tio n c y c le 0 PW M c y c le : 2 5 6 /fS
YS YS
5 0 /1 2 8
5 0 /1 2 8
5 0 /1 2 8
5 1 /1 2 8
5 0 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 2 /1 2 8
M o d u la tio n c y c le 1
M o d u la tio n c y c le 0
(7+1) PWM Mode
b7 b0 PW M AC R e g is te r v a lu e (7 + 1 ) M o d e
D C v a lu e
PWM Register for 7+1 Mode
* PWM Output Control
On all devices, the PWM outputs are pin-shared with the Port D I/O pins. To operate as PWM outputs and not as I/O pins, the correct PWM configuration options must be selected. A 0 must also be written to the corresponding bits in the I/O port control register PDC to ensure that the required PWM output pins are setup as outputs. After these two initial steps have been carried out, and of course after the required PWM value has been written into the PWM register, writing a 1 to the
corresponding bit in the PD output data register will enable the PWM data to appear on the pin. Writing a 0 to the corresponding bit in the PD output data register will disable the PWM output function and force the output low. In this way, the Port D data output register can be used as an on/off control for the PWM function. Note that if the configuration options have selected the PWM function, but a 1 has been written to its corresponding bit in the PDC control register to configure the pin as an input, then the pin can still function as a normal input line, with pull-high resistor options.
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The following sample program shows how the PWM outputs are setup and controlled, the corresponding PWM output configuration option must first be selected. clr PDC.0 clr PDC.1 clr PDC.2 clr PDC.3 set pd.0 mov a,64h mov pwm0,a set pd.1 mov a,65h mov pwm1,a set pd.2 mov a,66h mov pwm2,a set pd.3 mov a,67h mov pwm3,a clr pd.0 clr pd.1 clr pd.2 clr pd.3 ; set pin PD0 as output ; set pin PD1 as output ; set pin PD2 as output ; set pin PD3 as output ; PD.0=1; enable pin PD0/PWM0 to be the PWM channel 0 ; PWM0=100D=64H
; PD.1=1; enable pin PD1/PWM1 to be the PWM channel 1 ; PWM1=101D=65H
; PD.2=1; enable pin PD2/PWM2 to be the PWM channel 2 ; PWM2=102D=66H
; PD.3=1; enable pin PD3/PWM3 to be the PWM channel 3 ; PWM3=103D=67H
; disable PWM0 output - PD.0 will remain low ; disable PWM1 output - PD.1 will remain low ; disable PWM2 output - PD.2 will remain low ; disable PWM3 output - PD.3 will remain low
A/D Converter An eight channel and 12 bits resolution A/D converter is implemented in the microcontroller. The reference voltage is VDD. The A/D converter contains four special registers which are; ADRL (24H), ADRH (25H), ADCR (26H) and ACSR (27H). The ADRH and ADRL registers are the A/D result register higher-order byte and lower-order byte and are read-only. After the A/D conversion is completed, the ADRH and ADRL should be read to get the conversion result data. The ADCR is an A/D converter control register, which defines the A/D channel number, analog channel select, start A/D conversion control bit and the end of A/D conversion flag. To start an A/D conversion, the PB configuration must first be defined, the analog channel selected, after which the START bit can supply a rising and falling edge (0(R)1(R)0). At the end of A/D conversion, the EOCB bit is cleared. The ACSR register is the A/D clock setting register, which is used to select the A/D clock source. The A/D converter control register is used to control the A/D converter. Bit2~bit0 are used to select an analog input channel. There are a total of eight channels to select. Bit5~bit3 of the ADCR are used to set the PB configurations. PB can be an analog input or setup as a normal I/O line, the selected function is determined by these 3 bits. Once a PB line is selected as an analog input, the I/O function and pull-high resistor of this I/O line
are disabled and the A/D converter circuit is powered-on. The EOCB bit, bit6 of the ADCR is end of A/D conversion flag. This bit can be monitored to know when the A/D conversion has completed. The START bit in the ADCR register is used to start the conversion process of the A/D converter. Giving the START bit a rising edge and falling edge means that the A/D conversion has started. In order to ensure that the A/D conversion is completed, the START bit should remain at 0 until the EOCB flag is cleared to 0 which indicates the end of the A/D conversion. Bit 7 of the ACSR register is used for test purposes only and must not be used for other purposes by the application program. Bit1 and bit0 of the ACSR register are used to select the A/D clock source. The EOCB bit is set to 1 when the START bit is set from 0 to 1. Important Note for A/D initialisation: Special care must be taken to initialise the A/D converter each time the Port B A/D channel selection bits are modified, otherwise the EOCB flag may be in an undefined condition. An A/D initialisation is implemented by setting the START bit high and then clearing it to zero within 10 instruction cycles of the Port B channel selection bits being modified. Note that if the Port B channel selection bits are all cleared to zero then an A/D initialisation is not required. 28 July 10, 2006
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Bit No. Label Selects the A/D converter clock source 00=system clock/2 ADCS0 01=system clock/8 ADCS1 10=system clock/32 11=undefined 3/4 TEST Unused bit, read as 0 For test mode used only ACSR (27H) Register Bit No. Label ACS2, ACS1, ACS0: Select A/D channel 0, 0, 0: AN0 0, 0, 1: AN1 0, 1, 0: AN2 0, 1, 1: AN3 1, 0, 0: AN4 1, 0, 1: AN5 1, 1, 0: AN6 1, 1, 1: AN7 Defines the Port B configuration select. If PCR0, PCR1 and PCR2 are all zero, the ADC circuit is powered off to reduce power consumption. Indicates end of A/D conversion. (0 = end of A/D conversion) Each time bits 3~5 change state the A/D should be initialised by issuing a START signal, otherwise the EOCB flag may have an undefined condition. See Important note for A/D initialisation. Function Function
0 1
2~6 7
0 1 2
ACS0 ACS1 ACS2
3 4 5 6 7
PCR0 PCR1 PCR2 EOCB
START Starts the A/D conversion. (0(R)1(R)0= start; 0(R)1= Reset A/D converter and set EOCB to 1) ADCR (26H) Register
PCR2 0 0 0 0 1 1 1 1
PCR1 0 0 1 1 0 0 1 1
PCR0 0 1 0 1 0 1 0 1
7 PB7 PB7 PB7 PB7 PB7 PB7 PB7 AN7
6 PB6 PB6 PB6 PB6 PB6 PB6 PB6 AN6
5 PB5 PB5 PB5 PB5 PB5 PB5 AN5 AN5
4 PB4 PB4 PB4 PB4 PB4 AN4 AN4 AN4
3 PB3 PB3 PB3 PB3 AN3 AN3 AN3 AN3
2 PB2 PB2 PB2 AN2 AN2 AN2 AN2 AN2
1 PB1 PB1 AN1 AN1 AN1 AN1 AN1 AN1
0 PB0 AN0 AN0 AN0 AN0 AN0 AN0 AN0
Port B Configuration Register ADRL ADRH Bit7 D3 D11 Bit6 D2 D10 Bit5 D1 D9 Bit4 D0 D8 Bit3 3/4 D7 Bit2 3/4 D6 Bit1 3/4 D5 Bit0 3/4 D4
Note: D0~D11 is A/D conversion result data bit LSB~MSB. ADRL (24H), ADRH (25H) Register
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The following programming example illustrates how to setup and implement an A/D conversion. The method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete. Example: using EOCB Polling Method to detect end of conversion mov mov mov mov a,00000001B ACSR,a a,00100000B ADCR,a : : ; setup the ACSR register to select fSYS/8 as the A/D clock ; setup ADCR register to configure Port PB0~PB3 as A/D inputs ; and select AN0 to be connected to the A/D converter ; As the Port B channel bits have changed the following START ; signal (0-1-0) must be issued within 10 instruction cycles
: Start_conversion: clr START set START clr START Polling_EOC: sz EOCB jmp polling_EOC mov a,ADRH mov adrh_buffer,a mov a,ADRL mov adrl_buffer,a : : jmp start_conversion
; reset A/D ; start A/D ; poll the ADCR register EOCB bit to detect end of A/D conversion ; continue polling ; read conversion result high byte value from the ADRH register ; save result to user defined memory ; read conversion result low byte value from the ADRL register ; save result to user defined memory
; start next A/D conversion
M in im u m START
o n e in s tr u c tio n c y c le n e e d e d , M a x im u m
te n in s tr u c tio n c y c le s a llo w e d
EOCB PC R2~ PCR0
A /D tA 000B
DCS
s a m p lin g tim e 100B
A /D tA
DCS
s a m p lin g tim e
A /D tA
DCS
s a m p lin g tim e 000B 1 . P B p o rt s e tu p a s I/O s 2 . A /D c o n v e r te r is p o w e r e d o ff to r e d u c e p o w e r c o n s u m p tio n
100B
101B
AC S2~ ACS0
000B P o w e r-o n R eset R e s e t A /D c o n v e rte r 1 : D e fin e P B c o n fig u r a tio n 2 : S e le c t a n a lo g c h a n n e l A /D N o te : A /D tA D tA
CS
010B S ta rt o f A /D c o n v e r s io n
000B S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n
001B S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n
d o n 't c a r e
E n d o f A /D c o n v e r s io n tA D C c o n v e r s io n tim e
tA D C c o n v e r s io n tim e
YS
A /D
tA D C c o n v e r s io n tim e
A /D
DC
c lo c k m u s t b e fS = 3 2 tA D = 8 0 tA D
YS
/2 , fS
/8 o r fS
YS
/3 2
A/D Conversion Timing
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LCD Memory The device provides an area of embedded data memory for LCD display. This area is located from 40H to 6EH of the RAM at Bank 1. Bank pointer (BP; located at 04H of the RAM) is the switch between the RAM and the LCD display memory. When the BP is set as 1, any data written into 40H~6EH will affect the LCD display. When the BP is cleared to 0, 2 or 3, any data written into 40H~6EH is map into the general purpose data memory. The LCD display memory can be read and written to
COM 0 1 2 3 3 2 40H 41H 42H 43H 6CH 6DH 6EH B it 0 1
only by indirect addressing mode using MP1. When data is written into the display data area, it is automatically read by the LCD driver which then generates the corresponding LCD driving signals. To turn the display on or off, a 1 or a 0 is written to the corresponding bit of the display memory, respectively. The figure illustrates the mapping between the display memory and LCD pattern for the device. LCD Driver Output The output number of the device LCD driver can be 472 or 473 or 464 by option (i.e., 1/2 duty, 1/3 duty or 1/4 duty). The bias type LCD driver can be R type or C type. If the R bias type is selected, no external capacitor is required. If the C bias type is selected, a capacitor mounted between C1 and C2 pins is needed. The LCD driver bias voltage can be 1/2 bias or 1/3 bias by option. If 1/2 bias is selected, a capacitor mounted between V2 pin and ground is required. If 1/3 bias is selected, two capacitors are needed for V1 and V2 pins. Refer to application diagram.
SEGMENT
0
1
2
3
44
45
46
Display Memory
LCD Segments as Logical Output The SEG0~SEG23 also can be optioned as logical output, once an LCD segment is optioned as a logical output, the contents of bit0 of the related segment address in the LCD RAM will appear on the segment. SEG0~SEG7 are all byte optioned as logical outputs, SEG8~SEG15 are also byte optioned as logical outputs, SEG16~SEG23 are individually bit optioned as logical outputs. LCD Type LCD Bias Type VMAX R Type 1/2 bias 1/3 bias 1/2 bias C Type 1/3 bias 3 If VDD> VLCD, then VMAX connect to VDD, 2 else VMAX connect to V1
If VDD>VLCD, then VMAX connect to VDD, else VMAX connect to VLCD
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D u r in g a R e s e t P u ls e C O M 0 ,C O M 1 ,C O M 2 A ll L C D d r iv e r o u tp u ts * * * VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS is u s e d . CD S CD S VLC D VLC D
N o r m a l O p e r a tio n M o d e COM0 COM1 CO M 2* L C D s e g m e n ts O N C O M 0 ,1 , 2 s id e s a r e u n lig h te d O n ly L C D s e g m e n ts O N C O M 0 s id e a r e lig h te d O n ly L C D s e g m e n ts O N C O M 1 s id e a r e lig h te d O n ly L C D s e g m e n ts O N C O M 2 s id e a r e lig h te d L C D s e g m e n ts O N C O M 0 ,1 s id e s a r e lig h te d L C D s e g m e n ts O N C O M 0 , 2 s id e s a r e lig h te d L C D s e g m e n ts O N C O M 1 , 2 s id e s a r e lig h te d L C D s e g m e n ts O N C O M 0 ,1 , 2 s id e s a r e lig h te d HALT M ode CO M 0,CO M 1,CO M 2 A ll lc d d r iv e r o u tp u ts
CD CD S S
VLC D
VLC D VLC D VLC D VLC D VLC D VLC D VLC D VLC D
CD CD S S
CD CD S CD S S
CD S CD CD S
VLC D S CD VLC D S CD CD S S
VLC D VLC D
N o te : " * " O m it th e C O M 2 s ig n a l, if th e 1 /2 d u ty L C D
LCD Driver Output (1/3 Duty, 1/2 Byte, R/C Type)
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VA VB VC VSS VA VB VC COM1 VSS VA VB VC COM2 VSS VA VB COM3 VC VSS VA VB L C D s e g m e n ts O N C O M 2 s id e lig h te d N o te : 1 /4 d u ty , 1 /3 b ia s , C ty p e : " V A " 3 /2 V L C D , " V B " V L C D , " V C " 1 /2 V L C D VC VSS
COM0
1 /4 d u ty , 1 /3 b ia s , R ty p e : " V A " V L C D , " V B " 2 /3 V L C D , " V C " 1 /3 V L C D
LCD Driver Output
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Low Voltage Reset/Detector Functions There is a low voltage detector (LVD) and a low voltage reset circuit (LVR) implemented in this microcontroller. These two functions can be enabled/disabled by options. Once the LVD option is enabled, the user can use the RTCC.3 to enable/disable (1/0) the LVD circuit and read the LVD detector status (0/1) from RTCC.5, otherwise, the LVD function is disabled. The RTCC register definitions are listed below. Bit No. 0~2 3 4 5 6, 7 Note: Label RT0~RT2 LVDC* QOSC LVDO 3/4 Function 8 to 1 multiplexer control inputs to select the real clock prescaler output LVD enable/disable (1/0) 32768Hz OSC quick start-up oscillating 0/1: quick/slow start LVD detection output (1/0) 1: low voltage detected, read only Unused bit, read as 0
* Once the LVD function is enabled the reference generator should be enabled; otherwise the reference generator is controlled by LVR ROM code option. The relationship between LVR and LVD options and LVDC are as shown. RTCC (09H) Register The relationship between VDD and VLVR is shown below.
VDD 5 .5 V V
OPR
The LVR has the same effect or function with the external RES signal which performs a chip reset. During HALT state, both LVR and LVD are disabled. The LVR state requires the following specifications:
* The low voltage (0.9V~VLVR) has to be maintained for
5 .5 V
more than 1ms, otherwise, the circuits remain in their original state. If the low voltage state does not exceed 1ms, the LVR will ignore it and do not perform a reset function.
* The LVR uses the OR function with the external RES
V 3 .0 V 2 .2 V
LVR
signal to perform a chip reset.
0 .9 V
Note: VOPR is the voltage range for proper chip operation at 4MHz system clock.
V 5 .5 V
DD
V
LVR
LVR
D e te c t V o lta g e
0 .9 V 0V R e s e t S ig n a l
R eset *1
N o r m a l O p e r a tio n *2
R eset
Low Voltage Reset Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: Since low voltage state has to be maintained in its original state for over 1ms, therefore after 1ms delay, the device enters the reset mode. Rev. 1.00 34 July 10, 2006
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UART Bus Serial Interface The HT46RU66/HT46CU66 devices contain an integrated full-duplex asynchronous serial communications UART interface that enables communication with external devices that contain a serial interface. The UART function has many features and can transmit and receive data serially by transferring a frame of data with eight or nine data bits per transmission as well as being able to detect errors when the data is overwritten or incorrectly framed. The UART function possesses its own internal interrupt which can be used to indicate when a reception occurs or when a transmission terminates.
* UART features
which can also be used as a general purpose I/O pin, if the pin is not configured as a receiver, which occurs if the RXEN bit in the UCR2 register is equal to zero. Along with the UARTEN bit, the TXEN and RXEN bits, if set, will automatically setup these I/O pins to their respective TX output and RX input conditions and disable any pull-high resistor option which may exist on the RX pin.
* UART data transfer scheme
The integrated UART function contains the following features:

Full-duplex, asynchronous communication 8 or 9 bits character length Even, odd or no parity options One or two stop bits Baud rate generator with 8-bit prescaler Parity, framing, noise and overrun error detection Support for interrupt on address detect (last character bit=1) Separately enabled transmitter and receiver 2-byte Deep Fifo Receive Data Buffer Transmit and receive interrupts Interrupts can be initialized by the following conditions:
-

Transmitter Empty Transmitter Idle Receiver Full Receiver Overrun Address Mode Detect
The block diagram shows the overall data transfer structure arrangement for the UART. The actual data to be transmitted from the MCU is first transferred to the TXR register by the application program. The data will then be transferred to the Transmit Shift Register from where it will be shifted out, LSB first, onto the TX pin at a rate controlled by the Baud Rate Generator. Only the TXR register is mapped onto the MCU Data Memory, the Transmit Shift Register is not mapped and is therefore inaccessible to the application program. Data to be received by the UART is accepted on the external RX pin, from where it is shifted in, LSB first, to the Receiver Shift Register at a rate controlled by the Baud Rate Generator. When the shift register is full, the data will then be transferred from the shift register to the internal RXR register, where it is buffered and can be manipulated by the application program. Only the RXR register is mapped onto the MCU Data Memory, the Receiver Shift Register is not mapped and is therefore inaccessible to the application program. It should be noted that the actual register for data transmission and reception, although referred to in the text, and in application programs, as separate TXR and RXR registers, only exists as a single shared register in the Data Memory. This shared register known as the TXR/RXR register is used for both data transmission and data reception.
* UART status and control registers
* UART external pin interfacing
To communicate with an external serial interface, the internal UART has two external pins known as TX and RX. The TX pin is the UART transmitter pin, which can be used as a general purpose I/O pin if the pin is not configured as a UART transmitter, which occurs when the TXEN bit in the UCR2 control register is equal to zero. Similarly, the RX pin is the UART receiver pin,
T r a n s m itte r S h ift R e g is te r MSB LSB CLK TXR R e g is te r B a u d R a te G e n e ra to r T X P in
There are five control registers associated with the UART function. The USR, UCR1 and UCR2 registers control the overall function of the UART, while the BRG register controls the Baud rate. The actual data to be transmitted and received on the serial interface is managed through the TXR/RXR data registers.
R e c e iv e r S h ift R e g is te r R X P in CLK RXR R e g is te r B u ffe r MSB LSB
MCU
D a ta B u s
UART Data Transfer Scheme
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* USR register
The USR register is the status register for the UART, which can be read by the program to determine the present status of the UART. All flags within the USR register are read only. Further explanation on each of the flags is given below:
RXIF flag is cleared when the USR register is read with RXIF set, followed by a read from the RXR register, and if the RXR register has no data available.
TXIF The TXIF flag is the transmit data register empty flag. When this read only flag is 0 it indicates that the character is not transferred to the transmit shift registers. When the flag is 1 it indicates that the transmit shift register has received a character from the TXR data register. The TXIF flag is cleared by reading the UART status register (USR) with TXIF set and then writing to the TXR data register. Note that when the TXEN bit is set, the TXIF flag bit will also be set since the transmit buffer is not yet full. TIDLE The TIDLE flag is known as the transmission complete flag. When this read only flag is 0 it indicates that a transmission is in progress. This flag will be set to 1 when the TXIF flag is 1 and when there is no transmit data, or break character being transmitted. When TIDLE is 1 the TX pin becomes idle. The TIDLE flag is cleared by reading the USR register with TIDLE set and then writing to the TXR register. The flag is not generated when a data character, or a break is queued and ready to be sent. RXIF The RXIF flag is the receive register status flag. When this read only flag is 0 it indicates that the RXR read data register is empty. When the flag is 1 it indicates that the RXR read data register contains new data. When the contents of the shift register are transferred to the RXR register, an interrupt is generated if RIE=1 in the UCR2 register. If one or more errors are detected in the received word, the appropriate receive-related flags NF, FERR, and/or PERR are set within the same clock cycle. The
b7 PERR NF FERR OERR R ID L E R X IF T ID L E
b0
RIDLE The RIDLE flag is the receiver status flag. When this read only flag is 0 it indicates that the receiver is between the initial detection of the start bit and the completion of the stop bit. When the flag is 1 it indicates that the receiver is idle. Between the completion of the stop bit and the detection of the next start bit, the RIDLE bit is 1 indicating that the UART is idle. OERR The OERR flag is the overrun error flag, which indicates when the receiver buffer has overflowed. When this read only flag is 0 there is no overrun error. When the flag is 1 an overrun error occurs which will inhibit further transfers to the RXR receive data register. The flag is cleared by a software sequence, which is a read to the status register USR followed by an access to the RXR data register. FERR The FERR flag is the framing error flag. When this read only flag is 0 it indicates no framing error. When the flag is 1 it indicates that a framing error has been detected for the current character. The flag can also be cleared by a software sequence which will involve a read to the USR status register followed by an access to the RXR data register. NF The NF flag is the noise flag. When this read only flag is 0 it indicates a no noise condition. When the flag is 1 it indicates that the UART has detected noise on the receiver input. The NF flag is set during the same cycle as the RXIF flag but will not be set in the case of an overrun. The NF flag can be cleared by a software sequence which will involve a read to the USR status register, followed by an access to the RXR data register.
USR R e g is te r

T X IF
T r a n s m it d a ta r e g is te r e m p ty 1 : c h a r a c te r tr a n s fe r r e d to tr a n s m it s h ift r e g is te r 0 : c h a r a c te r n o t tr a n s fe r r e d to tr a n s m it s h ift r e g is te r T r a n s m is s io n id le 1 : n o tr a n s m is s io n in p r o g r e s s 0 : tr a n s m is s io n in p r o g r e s s R e c e iv e R X R r e g is te r s ta tu s 1 : R X R r e g is te r h a s a v a ila b le d a ta 0 : R X R r e g is te r is e m p ty R e c e iv e r s ta tu s 1 : r e c e iv e r is id le 0 : d a ta b e in g r e c e iv e d O v e rru n e rro r 1 : o v e rru n e rro r d e te c te d 0 : n o o v e rru n e rro r d e te c te d F r a m in g e r r o r fla g 1 : fr a m in g e r r o r d e te c te d 0 : n o fr a m in g e r r o r N o is e fla g 1 : n o is e d e te c te d 0 : n o n o is e d e te c te d P a r ity e r r o r fla g 1 : p a r ity e r r o r d e te c te d 0 : n o p a r ity e r r o r d e te c te d
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PERR The PERR flag is the parity error flag. When this read only flag is 0 it indicates that a parity error has not been detected. When the flag is 1 it indicates that the parity of the received word is incorrect. This error flag is applicable only if Parity mode (odd or even) is selected. The flag can also be cleared by a software sequence which involves a read to the USR status register, followed by an access to the RXR data register.
used, if the bit is equal to 0 then only one stop bit is used.
PRT This is the parity type selection bit. When this bit is equal to 1 odd parity will be selected, if the bit is equal to 0 then even parity will be selected. PREN This is parity enable bit. When this bit is equal to 1 the parity function will be enabled, if the bit is equal to 0 then the parity function will be disabled. BNO This bit is used to select the data length format, which can have a choice of either 8-bits or 9-bits. If this bit is equal to 1 then a 9-bit data length will be selected, if the bit is equal to 0 then an 8-bit data length will be selected. If 9-bit data length is selected then bits RX8 and TX8 will be used to store the 9th bit of the received and transmitted data respectively. UARTEN The UARTEN bit is the UART enable bit. When the bit is 0 the UART will be disabled and the RX and TX pins will function as General Purpose I/O pins. When the bit is 1 the UART will be enabled and the TX and RX pins will function as defined by the TXEN and RXEN control bits. When the UART is disabled it will empty the buffer so any character remaining in the buffer will be discarded. In addition, the baud rate counter value will be reset. When the UART is disabled, all error and status flags will be reset. The TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR, and NF bits will be cleared, while the TIDLE, TXIF and RIDLE bits will be set. Other control bits in UCR1, UCR2, and BRG registers will remain unaffected. If the UART is active and the UARTEN bit is cleared, all pending transmissions and receptions will be terminated and the module will be reset as defined above. When the UART is re-enabled it will restart in the same configuration.
* UCR1 register
The UCR1 register together with the UCR2 register are the two UART control registers that are used to set the various options for the UART function, such as overall on/off control, parity control, data transfer bit length etc. Further explanation on each of the bits is given below:
TX8 This bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the transmitted data, known as TX8. The BNO bit is used to determine whether data transfers are in 8-bit or 9-bit format. RX8 This bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the received data, known as RX8. The BNO bit is used to determine whether data transfers are in 8-bit or 9-bit format. TXBRK The TXBRK bit is the Transmit Break Character bit. When this bit is 0 there are no break characters and the TX pin operates normally. When the bit is 1 there are transmit break characters and the transmitter will send logic zeros. When equal to 1 after the buffered data has been transmitted, the transmitter output is held low for a minimum of a 13-bit length and until the TXBRK bit is reset. STOPS This bit determines if one or two stop bits are to be used. When this bit is equal to 1 two stop bits are
b7 UARTEN BNO PREN PRT STOPS TXBRK RX8
b0

TX8
U C R 1 R e g is te r T r a n s m it d a ta b it 8 ( w r ite o n ly ) R e c e iv e d a ta b it 8 ( r e a d o n ly ) T r a n s m it b r e a k c h a r a c te r 1 : tr a n s m it b r e a k c h a r a c te r s 0 : n o b re a k c h a ra c te rs D e fin e s th e n u m b e r o f s to p b its 1 : tw o s to p b its 0 : o n e s to p b it P a r ity ty p e b it 1 : o d d p a r ity fo r p a r ity g e n e r a to r 0 : e v e n p a r ity fo r p a r ity g e n e r a to r P a r ity e n a b le b it 1 : p a r ity fu n c tio n e n a b le d 0 : p a r ity fu n c tio n d is a b le d N u m b e r o f d a ta tr a n s fe r b its 1 : 9 - b it d a ta tr a n s fe r 0 : 8 - b it d a ta tr a n s fe r U A R T e n a b le b it 1 : e n a b le U A R T , T X & R X p in s a s U A R T p in s 0 : d is a b le U A R T , T X & R X p in s a s I/O p o r t p in s
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* UCR2 register
The UCR2 register is the second of the two UART control registers and serves several purposes. One of its main functions is to control the basic enable/disable operation of the UART Transmitter and Receiver as well as enabling the various UART interrupt sources. The register also serves to control the baud rate speed, receiver wake-up enable and the address detect enable. Further explanation on each of the bits is given below:
to 0 and if the MCU is in the Power Down Mode, any edge transitions on the RX pin will not wake-up the device.
TEIE This bit enables or disables the transmitter empty interrupt. If this bit is equal to 1 when the transmitter empty TXIF flag is set, due to a transmitter empty condition, the UART interrupt request flag will be set. If this bit is equal to 0 the UART interrupt request flag will not be influenced by the condition of the TXIF flag. TIIE This bit enables or disables the transmitter idle interrupt. If this bit is equal to 1 when the transmitter idle TIDLE flag is set, the UART interrupt request flag will be set. If this bit is equal to 0 the UART interrupt request flag will not be influenced by the condition of the TIDLE flag. RIE This bit enables or disables the receiver interrupt. If this bit is equal to 1 when the receiver overrun OERR flag or receive data available RXIF flag is set, the UART interrupt request flag will be set. If this bit is equal to 0 the UART interrupt will not be influenced by the condition of the OERR or RXIF flags. WAKE This bit enables or disables the receiver wake-up function. If this bit is equal to 1 and if the MCU is in the Power Down Mode, a low going edge on the RX input pin will wake-up the device. If this bit is equal
b7 TXEN RXEN BRGH ADDEN W AKE R IE T IIE
b0
ADDEN The ADDEN bit is the address detect mode bit. When this bit is 1 the address detect mode is enabled. When this occurs, if the 8th bit, which corresponds to RX7 if BNO=0, or the 9th bit, which corresponds to RX8 if BNO=1, has a value of 1 then the received word will be identified as an address, rather than data. If the corresponding interrupt is enabled, an interrupt request will be generated each time the received word has the address bit set, which is the 8 or 9 bit depending on the value of BNO. If the address bit is 0 an interrupt will not be generated, and the received data will be discarded. BRGH The BRGH bit selects the high or low speed mode of the Baud Rate Generator. This bit, together with the value placed in the BRG register, controls the Baud Rate of the UART. If this bit is equal to 1 the high speed mode is selected. If the bit is equal to 0 the low speed mode is selected. RXEN The RXEN bit is the Receiver Enable Bit. When this bit is equal to 0 the receiver will be disabled with any pending data receptions being aborted. In addition the buffer will be reset. In this situation the RX pin can be used as a general purpose I/O pin. If the RXEN bit is equal to 1 the receiver will be enabled and if the UARTEN bit is equal to 1 the RX pin will be controlled by the UART. Clearing the RXEN bit during a transmission will cause the data reception to be aborted and will reset the receiver. If this occurs, the RX pin can be used as a general purpose I/O pin.

T E IE
U C R 2 R e g is te r T r a n s m itte r e m p ty in te r r u p t e n a b le 1 : T X IF in te r r u p t r e q u e s t e n a b le 0 : T X IF in te r r u p t r e q u e s t d is a b le T r a n s m itte r id le in te r r u p t e n a b le 1 : T ID L E in te r r u p t r e q u e s t e n a b le 0 : T ID L E in te r r u p t r e q u e s t d is a b le R e c e iv e r in te r r u p t e n a b le 1 : R X IF in te r r u p t r e q u e s t e n a b le 0 : R X IF in te r r u p t r e q u e s t d is a b le D e fin e s th e R X w a k e u p e n a b le 1 : R X w a k e u p e n a b le ( fa llin g e d g e ) 0 : R X w a k e u p d is a b le A d d re s s d e te c t m o d e 1 : e n a b le 0 : d is a b le H ig h b a u d r a te s e le c t b it 1 : h ig h s p e e d 0 : lo w s p e e d R e c e iv e r e n a b le b it 1 : r e c e iv e r e n a b le 0 : r e c e iv e r d is a b le T r a n s m itte r e n a b le b it 1 : tr a n s m itte r e n a b le 0 : tr a n s m itte r d is a b le
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TXEN The TXEN bit is the Transmitter Enable Bit. When this bit is equal to 0 the transmitter will be disabled with any pending transmissions being aborted. In addition the buffer will be reset. In this situation the TX pin can be used as a general purpose I/O pin. If the TXEN bit is equal to 1 the transmitter will be enabled and if the UARTEN bit is equal to 1 the TX pin will be controlled by the UART. Clearing the TXEN bit during a transmission will cause the transmission to be aborted and will reset the transmitter. If this occurs, the TX pin can be used as a general purpose I/O pin.
By programming the BRGH bit which allows selection of the related formula and programming the required value in the BRG register, the required baud rate can be setup. Note that because the actual baud rate is determined using a discrete value, N, placed in the BRG register, there will be an error associated between the actual and requested value. The following example shows how the BRG register value N and the error value can be calculated. Calculating the register and error values For a clock frequency of 8MHz, and with BRGH set to 0 determine the BRG register value N, the actual baud rate and the error value for a desired baud rate of 9600. From the above table the desired baud rate BR fSYS = [64 (N + 1)] fSYS Re-arranging this equation gives N = -1 (BRx64) 8000000 - 1 = 12.0208 Giving a value for N = (9600x 64) To obtain the closest value, a decimal value of 12 should be placed into the BRG register. This gives an actual or calculated baud rate value of 8000000 BR = = 9615 [64(12 + 1)] Therefore the error is equal to
9615
* Baud rate generator
To setup the speed of the serial data communication, the UART function contains its own dedicated baud rate generator. The baud rate is controlled by its own internal free running 8-bit timer, the period of which is determined by two factors. The first of these is the value placed in the BRG register and the second is the value of the BRGH bit within the UCR2 control register. The BRGH bit decides, if the baud rate generator is to be used in a high speed mode or low speed mode, which in turn determines the formula that is used to calculate the baud rate. The value in the BRG register determines the division factor, N, which is used in the following baud rate calculation formula. Note that N is the decimal value placed in the BRG register and has a range of between 0 and 255. UCR2 BRGH Bit Baud Rate 0 fSYS [64 (N + 1)] 1 fSYS [16 (N + 1)]
9600
9600
= 0.16%
The following tables show actual values of baud rate and error values for the two values of BRGH. Baud Rate K/BPS 0.3 1.2 2.4 4.8 9.6 19.2 38.4 57.6 115.2 Baud Rates for BRGH=0 fSYS=8MHz BRG 3/4 103 51 25 12 6 2 1 0 Kbaud 3/4 1.202 2.404 4.807 9.615 17.857 41.667 62.5 125 Error 3/4 0.16 0.16 0.16 0.16 -6.99 8.51 8.51 8.51 fSYS=7.159MHz BRG 3/4 92 46 22 11 5 2 1 0 Kbaud 3/4 1.203 2.38 4.863 9.322 18.64 37.29 55.93 111.86 Error 3/4 0.23 -0.83 1.32 -2.9 -2.9 -2.9 -2.9 -2.9 BRG 207 51 25 12 6 2 1 0 3/4 fSYS=4MHz Kbaud 0.300 1.202 2.404 4.808 8.929 20.83 3/4 62.5 3/4 Error 0.00 0.16 0.16 0.16 -6.99 8.51 3/4 8.51 3/4 fSYS=3.579545MHz BRG 185 46 22 11 5 2 1 0 3/4 Kbaud 0.300 1.19 2.432 4.661 9.321 18.643 3/4 55.93 3/4 Error 0.00 -0.83 1.32 -2.9 -2.9 -2.9 3/4 -2.9 3/4
Baud Rates and Error Values for BRGH = 0
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Baud Rate K/BPS 0.3 1.2 2.4 4.8 9.6 19.2 38.4 57.6 115.2 250 Baud Rates for BRGH=1 fSYS=8MHz BRG 3/4 3/4 207 103 51 25 12 8 3 1 Kbaud 3/4 3/4 2.404 4.808 9.615 19.231 38.462 55.556 125 250 Error 3/4 3/4 0.16 0.16 0.16 0.16 0.16 -3.55 8.51 0 fSYS=7.159MHz BRG 3/4 3/4 185 92 46 22 11 7 3 3/4 Kbaud 3/4 3/4 2.405 4.811 9.520 19.454 37.287 55.93 111.86 3/4 Error 3/4 3/4 0.23 0.23 -0.832 1.32 -2.9 -2.9 -2.9 3/4 BRG 3/4 207 103 51 25 12 6 3 1 0 fSYS=4MHz Kbaud 3/4 1.202 2.404 4.808 9.615 19.231 35.714 62.5 125 250 Error 3/4 0.16 0.16 0.16 0.16 0.16 -6.99 8.51 8.51 0 fSYS=3.579545MHz BRG 3/4 185 92 46 22 11 5 3 1 3/4 Kbaud 3/4 1.203 2.406 4.76 9.727 18.643 37.286 55.930 111.86 3/4 Error 3/4 0.23 0.23 -0.83 1.32 -2.9 -2.9 -2.9 -2.9 3/4
Baud Rates and Error Values for BRGH = 1
* Setting up and controlling the UART
Introduction For data transfer, the UART function utilizes a non-return-to-zero, more commonly known as NRZ, format. This is composed of one start bit, eight or nine data bits, and one or two stop bits. Parity is supported by the UART hardware, and can be setup to be even, odd or no parity. For the most common data format, 8 data bits along with no parity and one stop bit, denoted as 8, N, 1, is used as the default setting, which is the setting at power-on. The number of data bits and stop bits, along with the parity, are setup by programming the corresponding BNO, PRT, PREN, and STOPS bits in the UCR1 register. The baud rate used to transmit and receive data is setup using the internal 8-bit baud rate generator, while the data is transmitted and received LSB first. Although the UARTs transmitter and receiver are functionally independent, they both use the same data format and baud rate. In all cases stop bits will be used for data transmission. Enabling/disabling the UART The basic on/off function of the internal UART function is controlled using the UARTEN bit in the UCR1 register. As the UART transmit and receive pins, TX and RX respectively, are pin-shared with normal I/O pins, one of the basic functions of the UARTEN control bit is to control the UART function of these two pins. If the UARTEN, TXEN and RXEN bits are set, then these two I/O pins will be setup as a TX output pin and an RX input pin respectively, in effect disabling the normal I/O pin function. If no data is being transmitted on the TX pin then it will default to a logic high value.
Clearing the UARTEN bit will disable the TX and RX pins and allow these two pins to be used as normal I/O pins. When the UART function is disabled the buffer will be reset to an empty condition, at the same time discarding any remaining residual data. Disabling the UART will also reset the error and status flags with bits TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR and NF being cleared while bits TIDLE, TXIF and RIDLE will be set. The remaining control bits in the UCR1, UCR2 and BRG registers will remain unaffected. If the UARTEN bit in the UCR1 register is cleared while the UART is active, then all pending transmissions and receptions will be immediately suspended and the UART will be reset to a condition as defined above. If the UART is then subsequently re-enabled, it will restart again in the same configuration.
Data, parity and stop bit selection The format of the data to be transferred, is composed of various factors such as data bit length, parity on/off, parity type, address bits and the number of stop bits. These factors are determined by the setup of various bits within the UCR1 register. The BNO bit controls the number of data bits which can be set to either 8 or 9, the PRT bit controls the choice of odd or even parity, the PREN bit controls the parity on/off function and the STOPS bit decides whether one or two stop bits are to be used. The following table shows various formats for data transmission. The address bit identifies the frame as an address character. The number of stop bits, which can be either one or two, is independent of the data length.
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Start Bit Data Bits Address Bits Parity Bits Stop Bit
Example of 8-bit Data Formats 1 1 1 8 7 7 0 0 1
1
0 1 0
1 1 1
Example of 9-bit Data Formats 1 1 1 9 8 8 0 0 11 0 1 0 1 1 1
Transmitting data When the UART is transmitting data, the data is shifted on the TX pin from the shift register, with the least significant bit first. In the transmit mode, the TXR register forms a buffer between the internal bus and the transmitter shift register. It should be noted that if 9-bit data format has been selected, then the MSB will be taken from the TX8 bit in the UCR1 register. The steps to initiate a data transfer can be summarized as follows:
-
Make the correct selection of the BNO, PRT, PREN and STOPS bits to define the required word length, parity type and number of stop bits. Setup the BRG register to select the desired baud rate. Set the TXEN bit to ensure that the TX pin is used as a UART transmitter pin and not as an I/O pin. Access the USR register and write the data that is to be transmitted into the TXR register. Note that this step will clear the TXIF bit. This sequence of events can now be repeated to send additional data.
-
Transmitter Receiver Data Format The following diagram shows the transmit and receive waveforms for both 8-bit and 9-bit data formats.
* UART transmitter
Data word lengths of either 8 or 9 bits, can be selected by programming the BNO bit in the UCR1 register. When BNO bit is set, the word length will be set to 9 bits. In this case the 9th bit, which is the MSB, needs to be stored in the TX8 bit in the UCR1 register. At the transmitter core lies the Transmitter Shift Register, more commonly known as the TSR, whose data is obtained from the transmit data register, which is known as the TXR register. The data to be transmitted is loaded into this TXR register by the application program. The TSR register is not written to with new data until the stop bit from the previous transmission has been sent out. As soon as this stop bit has been transmitted, the TSR can then be loaded with new data from the TXR register, if it is available. It should be noted that the TSR register, unlike many other registers, is not directly mapped into the Data Memory area and as such is not available to the application program for direct read/write operations. An actual transmission of data will normally be enabled when the TXEN bit is set, but the data will not be transmitted until the TXR register has been loaded with data and the baud rate generator has defined a shift clock source. However, the transmission can also be initiated by first loading data into the TXR register, after which the TXEN bit can be set. When a transmission of data begins, the TSR is normally empty, in which case a transfer to the TXR register will result in an immediate transfer to the TSR. If during a transmission the TXEN bit is cleared, the transmission will immediately cease and the transmitter will be reset. The TX output pin will then return to having a normal general purpose I/O pin function.
-
It should be noted that when TXIF=0, data will be inhibited from being written to the TXR register. Clearing the TXIF flag is always achieved using the following software sequence: 1. A USR register access 2. A TXR register write execution The read-only TXIF flag is set by the UART hardware and if set indicates that the TXR register is empty and that other data can now be written into the TXR register without overwriting the previous data. If the TEIE bit is set then the TXIF flag will generate an interrupt. During a data transmission, a write instruction to the TXR register will place the data into the TXR register, which will be copied to the shift register at the end of the present transmission. When there is no data transmission in progress, a write instruction to the TXR register will place the data directly into the shift register, resulting in the commencement of data transmission, and the TXIF bit being immediately set. When a frame transmission is complete, which happens after stop bits are sent or after the break frame, the TIDLE bit will be set. To clear the TIDLE bit the following software sequence is used: 1. A USR register access 2. A TXR register write execution Note that both the TXIF and TIDLE bits are cleared by the same software sequence.
P a r ity B it S ta r t B it B it 0 B it 1 B it 2 B it 3 B it 4 B it 5 B it 6 B it 7 S to p B it
N ext S ta rt B it
8 -B it D a ta F o r m a t P a r ity B it S ta r t B it B it 0 B it 1 B it 2 B it 3 B it 4 B it 5 B it 6 B it 7 B it 8 S to p B it N ext S ta rt B it
9 -B it D a ta F o r m a t
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Transmit break If the TXBRK bit is set then break characters will be sent on the next transmission. Break character transmission consists of a start bit, followed by 13 N 0 bits and stop bits, where N=1, 2, etc. If a break character is to be transmitted then the TXBRK bit must be first set by the application program, then cleared to generate the stop bits. Transmitting a break character will not generate a transmit interrupt. Note that a break condition length is at least 13 bits long. If the TXBRK bit is continually kept at a logic high level then the transmitter circuitry will transmit continuous break characters. After the application program has cleared the TXBRK bit, the transmitter will finish transmitting the last break character and subsequently send out one or two stop bits. The automatic logic highs at the end of the last break character will ensure that the start bit of the next frame is recognized.
-
Set the RXEN bit to ensure that the RX pin is used as a UART receiver pin and not as an I/O pin.
At this point the receiver will be enabled which will begin to look for a start bit. When a character is received the following sequence of events will occur: - The RXIF bit in the USR register will be set when RXR register has data available, at least one more character can be read.
-
When the contents of the shift register have been transferred to the RXR register, then if the RIE bit is set, an interrupt will be generated. If during reception, a frame error, noise error, parity error, or an overrun error has been detected, then the error flags can be set.
-
* UART receiver
The RXIF bit can be cleared using the following software sequence: 1. A USR register access 2. An RXR register read execution
Introduction The UART is capable of receiving word lengths of either 8 or 9 bits. If the BNO bit is set, the word length will be set to 9 bits with the MSB being stored in the RX8 bit of the UCR1 register. At the receiver core lies the Receive Serial Shift Register, commonly known as the RSR. The data which is received on the RX external input pin, is sent to the data recovery block. The data recovery block operating speed is 16 times that of the baud rate, while the main receive serial shifter operates at the baud rate. After the RX pin is sampled for the stop bit, the received data in RSR is transferred to the receive data register, if the register is empty. The data which is received on the external RX input pin is sampled three times by a majority detect circuit to determine the logic level that has been placed onto the RX pin. It should be noted that the RSR register, unlike many other registers, is not directly mapped into the Data Memory area and as such is not available to the application program for direct read/write operations. Receiving data When the UART receiver is receiving data, the data is serially shifted in on the external RX input pin, LSB first. In the read mode, the RXR register forms a buffer between the internal bus and the receiver shift register. The RXR register is a two byte deep FIFO data buffer, where two bytes can be held in the FIFO while a third byte can continue to be received. Note that the application program must ensure that the data is read from RXR before the third byte has been completely shifted in, otherwise this third byte will be discarded and an overrun error OERR will be subsequently indicated. The steps to initiate a data transfer can be summarized as follows:
-
Receive break Any break character received by the UART will be managed as a framing error. The receiver will count and expect a certain number of bit times as specified by the values programmed into the BNO and STOPS bits. If the break is much longer than 13 bit times, the reception will be considered as complete after the number of bit times specified by BNO and STOPS. The RXIF bit is set, FERR is set, zeros are loaded into the receive data register, interrupts are generated if appropriate and the RIDLE bit is set. If a long break signal has been detected and the receiver has received a start bit, the data bits and the invalid stop bit, which sets the FERR flag, the receiver must wait for a valid stop bit before looking for the next start bit. The receiver will not make the assumption that the break condition on the line is the next start bit. A break is regarded as a character that contains only zeros with the FERR flag set. The break character will be loaded into the buffer and no further data will be received until stop bits are received. It should be noted that the RIDLE read only flag will go high when the stop bits have not yet been received. The reception of a break character on the UART registers will result in the following:
-
The framing error flag, FERR, will be set. The receive data register, RXR, will be cleared. The OERR, NF, PERR, RIDLE or RXIF flags will possibly be set.
Make the correct selection of BNO, PRT, PREN and STOPS bits to define the word length, parity type and number of stop bits. Setup the BRG register to select the desired baud rate.
-
Idle status When the receiver is reading data, which means it will be in between the detection of a start bit and the reading of a stop bit, the receiver status flag in the USR register, otherwise known as the RIDLE flag, will have a zero value. In between the reception of a stop bit and the detection of the next start bit, the RIDLE flag will have a high value, which indicates the receiver is in an idle condition.
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Receiver interrupt The read only receive interrupt flag RXIF in the USR register is set by an edge generated by the receiver. An interrupt is generated if RIE=1, when a word is transferred from the Receive Shift Register, RSR, to the Receive Data Register, RXR. An overrun error can also generate an interrupt if RIE=1.
-
No interrupt will be generated. However this bit rises at the same time as the RXIF bit which itself generates an interrupt. Note that the NF flag is reset by a USR register read operation followed by an RXR register read operation.
* Managing receiver errors
Several types of reception errors can occur within the UART module, the following section describes the various types and how they are managed by the UART.
Overrun Error - OERR flag The RXR register is composed of a two byte deep FIFO data buffer, where two bytes can be held in the FIFO register, while a third byte can continue to be received. Before this third byte has been entirely shifted in, the data should be read from the RXR register. If this is not done, the overrun error flag OERR will be consequently indicated. In the event of an overrun error occurring, the following will happen:
-
Framing Error - FERR Flag The read only framing error flag, FERR, in the USR register, is set if a zero is detected instead of stop bits. If two stop bits are selected, both stop bits must be high, otherwise the FERR flag will be set. The FERR flag is buffered along with the received data and is cleared on any reset. Parity Error - PERR Flag The read only parity error flag, PERR, in the USR register, is set if the parity of the received word is incorrect. This error flag is only applicable if the parity is enabled, PREN = 1, and if the parity type, odd or even is selected. The read only PERR flag is buffered along with the received data bytes. It is cleared on any reset. It should be noted that the FERR and PERR flags are buffered along with the corresponding word and should be read before reading the data word.
The OERR flag in the USR register will be set. The RXR contents will not be lost. The shift register will be overwritten.
* UART interrupt scheme
An interrupt will be generated if the RIE bit is set. The OERR flag can be cleared by an access to the USR register followed by a read to the RXR register.
Noise Error - NF Flag Over-sampling is used for data recovery to identify valid incoming data and noise. If noise is detected within a frame the following will occur:
-
The read only noise flag, NF, in the USR register will be set on the rising edge of the RXIF bit. Data will be transferred from the Shift register to the RXR register.
The UART internal function possesses its own internal interrupt and independent interrupt vector. Several individual UART conditions can generate an internal UART interrupt. These conditions are, a transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address detect and an RX pin wake-up. When any of these conditions are created, if the UART interrupt is enabled and the stack is not full, the program will jump to the UART interrupt vector where it can be serviced before returning to the main program. Four of these conditions, have a corresponding USR register flag, which will generate a UART interrupt if its associated interrupt enable flag in
USR
R e g is te r
U C R 2 R e g is te r T E IE 1 0 IN T C 1 R e g is te r 0 1 R IE 1 0 U A R T In te rru p t R e q u e s t F la g URF EURI IN T C 0 R e g is te r EMI
T r a n s m itte r E m p ty F la g T X IF
T r a n s m itte r Id le F la g T ID L E
T IIE
R e c e iv e r O v e r r u n F la g O E R R
OR
R e c e iv e r D a ta A v a ila b le R X IF
ADDEN
1
0 0 1
R X P in W a k e -u p
W AKE 1
0
R X 7 if B N O = 0 R X 8 if B N O = 1
U C R 2 R e g is te r
UART Interrupt Scheme
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the UCR2 register is set. The two transmitter interrupt conditions have their own corresponding enable bits, while the two receiver interrupt conditions have a shared enable bit. These enable bits can be used to mask out individual UART interrupt sources. The address detect condition, which is also a UART interrupt source, does not have an associated flag, but will generate a UART interrupt when an address detect condition occurs if its function is enabled by setting the ADDEN bit in the UCR2 register. An RX pin wake-up, which is also a UART interrupt source, does not have an associated flag, but will generate a UART interrupt if the microcontroller is woken up by a low going edge on the RX pin, if the WAKE and RIE bits in the UCR2 register are set. Note that in the event of an RX wake-up interrupt occurring, there will be a delay of 1024 system clock cycles before the system resumes normal operation. Note that the USR register flags are read only and cannot be cleared or set by the application program, neither will they be cleared when the program jumps to the corresponding interrupt servicing routine, as is the case for some of the other interrupts. The flags will be cleared automatically when certain actions are taken by the UART, the details of which are given in the UART register section. The overall UART interrupt can be disabled or enabled by the EURI bit in the INTC1 interrupt control register to prevent a UART interrupt from occurring.
* Address detect mode
exclusive functions. Therefore if the address detect mode is enabled, then to ensure correct operation, the parity function should be disabled by resetting the parity enable bit to zero. ADDEN 0 1 0 1 1 ADDEN Bit Function
* UART operation in power down mode
Bit 9 if BNO=1, UART Interrupt Bit 8 if BNO=0 Generated 0 O O X O
Setting the Address Detect Mode bit, ADDEN, in the UCR2 register, enables this special mode. If this bit is enabled then an additional qualifier will be placed on the generation of a Receiver Data Available interrupt, which is requested by the RXIF flag. If the ADDEN bit is enabled, then when data is available, an interrupt will only be generated, if the highest received bit has a high value. Note that the EURI and EMI interrupt enable bits must also be enabled for correct interrupt generation. This highest address bit is the 9th bit if BNO=1 or the 8th bit if BNO=0. If this bit is high, then the received word will be defined as an address rather than data. A Data Available interrupt will be generated every time the last bit of the received word is set. If the ADDEN bit is not enabled, then a Receiver Data Available interrupt will be generated each time the RXIF flag is set, irrespective of the data last bit status. The address detect mode and parity enable are mutually
When the MCU is in the Power Down Mode the UART will cease to function. When the device enters the Power Down Mode, all clock sources to the module are shutdown. If the MCU enters the Power Down Mode while a transmission is still in progress, then the transmission will be terminated and the external TX transmit pin will be forced to a logic high level. In a similar way, if the MCU enters the Power Down Mode while receiving data, then the reception of data will likewise be terminated. When the MCU enters the Power Down Mode, note that the USR, UCR1, UCR2, transmit and receive registers, as well as the BRG register will not be affected. The UART function contains a receiver RX pin wake-up function, which is enabled or disabled by the WAKE bit in the UCR2 register. If this bit, along with the UART enable bit, UARTEN, the receiver enable bit, RXEN and the receiver interrupt bit, RIE, are all set before the MCU enters the Power Down Mode, then a falling edge on the RX pin will wake-up the MCU from the Power Down Mode. Note that as it takes 1024 system clock cycles after a wake-up, before normal microcontroller operation resumes, any data received during this time on the RX pin will be ignored. For a UART wake-up interrupt to occur, in addition to the bits for the wake-up being set, the global interrupt enable bit, EMI, and the UART interrupt enable bit, EURI must also be set. If these two bits are not set then only a wake up event will occur and no interrupt will be generated. Note also that as it takes 1024 system clock cycles after a wake-up before normal microcontroller resumes, the UART interrupt will not be generated until after this time has elapsed.
Options The following shows the options in the device. All these options should be defined in order to ensure having a proper functioning system. Options OSC type selection. This option is to determine if an RC or crystal or 32768Hz crystal oscillator is chosen as system clock. WDT, RTC and time base clock source selection. There are three types of selections: system clock/4 or RTC OSC or WDT OSC.
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Options WDT enable/disable selection. WDT can be enabled or disabled by option. WDT time-out period selection. There are four types of selection: WDT clock source divided by 212/fS~213/fS, 213/fS~214/fS, 214/fS~215/fS or 215/fS~216/fS. CLR WDT times selection. This option defines the method to clear the WDT by instruction. One time means that the CLR WDT can clear the WDT. Two times means only if both of the CLR WDT1 and CLR WDT2 have been executed, only then can the WDT be cleared. Time Base time-out period selection. The Time Base time-out period ranges from clock/212 to clock/215. clock means the clock source selected by options. Buzzer output frequency selection. There are eight types of frequency signals for the buzzer output: clock/22 ~ clock/29. clock means the clock source selected by options. Wake-up selection. This option defines the wake-up capability. External I/O pins (PA only) all have the capability to wake-up the chip from a HALT by a falling edge (bit option). Pull-high selection. This option is to determine whether the pull-high resistance is viable or not in the input mode of the I/O ports. PA, PB, PC and PD can be independently selected (bit option). I/O pins share with other function selections. PA0/BZ, PA1/BZ: PA0 and PA1 can be set as I/O pins or buzzer outputs. PA3/PFD: PA3 can be set as I/O pins or PFD output. LCD common selection. There are three types of selections: 2 common (1/2 duty) or 3 common (1/3 duty) or 4 common (1/4 duty). If the 4 common is selected, the segment output pin SEG46 will be set as a common output. LCD bias power supply selection. There are two types of selections: 1/2 bias or 1/3 bias LCD bias type selection. This option is to determine what kind of bias is selected, R type or C type (Low or high bias current option). LCD driver clock frequency selection. There are seven types of frequency signals for the LCD driver circuits: fS/22~fS/28. fS stands for the clock source selection by options. LCD ON/OFF at HALT selection. LCD Segments as logical output selection, (byte, byte, bit, bit, bit, bit, bit, bit, bit, bit option) [SEG0~SEG7], [SEG8~SEG15], SEG16, SEG17, SEG18, SEG19, SEG20, SEG21, SEG22, or SEG23 LVR selection. LVR has enable or disable options LVD selection. LVD has enable or disable options PFD selection. If PA3 is set as PFD output, there are two types of selections; One is PFD0 as the PFD output, the other is PFD1 as the PFD output. PFD0, PFD1 are the timer overflow signals of the Timer/Event Counter 0, Timer/Event Counter 1 respectively. PWM selection: (7+1) or (6+2) mode PD0: level output or PWM0 output PD1: level output or PWM1 output PD2: level output or PWM2 output PD3: level output or PWM3 output INT0 or INT1 triggering edge selection: disable; high to low; low to high; low to high or high to low.
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Application Circuits
V
DD
0 .0 1 m F * 100kW 0 .1 m F
10kW
VDD RES
CO M 0~CO M 2 C O M 3 /S E G 4 6 SEG 0~SEG 45 VLC D VMAX
LCD Panel LCD LCD P o w e r S u p p ly H ig h V o lta g e
0 .1 m F * VSS
C1 0 .1 m F C2
OSC C ir c u it S e e r ig h t s id e 32768H z
OSC1 OSC2
V1 0 .1 m F V2 0 .1 m F V
DD
470pF R
OSC
OSC1 fS
YS
R C S y s te m O s c illa to r 24kW /4
OSC3 P A 0 /B P A 1 /B PA P A 3 /P F PA4~PA D 7 ~ Z Z 2
OSC2 OSC1 C ry s ta l S y s te m F o r th e v a lu e s , s e e ta b le b e lo w O s c illa to r
C1
OSC4 P D 0 /P W M 0 P D 3 /P W M 3 P D 4 /IN T 0 P D 5 /IN T 1 P D 6 /T M R 0 P D 7 /T M R 1 ~
C2 R1
OSC2
P B 0 /A N 0 P B 7 /A N 7 P C 0 /T PC 1~ PC PC MR PC 6 /T 7 /R X 2 X 5
OSC1
OSC2
3 2 7 6 8 H z C ry s ta l S y s te m O s c illa to r O S C 1 a n d O S C 2 le ft u n c o n n e c te d
H T 4 6 R U 6 6 /H T 4 6 C U 6 6
O S C C ir c u it
The following table shows the C1, C2 and R1 values corresponding to the different crystal values. (For reference only) Crystal or Resonator 4MHz Crystal 4MHz Resonator 3.58MHz Crystal 3.58MHz Resonator 2MHz Crystal & Resonator 1MHz Crystal 480kHz Resonator 455kHz Resonator 429kHz Resonator C1, C2 0pF 10pF 0pF 25pF 25pF 35pF 300pF 300pF 300pF R1 10kW 12kW 10kW 10kW 10kW 27kW 9.1kW 10kW 10kW
The function of the resistor R1 is to ensure that the oscillator will switch off should low voltage conditions occur. Such a low voltage, as mentioned here, is one which is less than the lowest value of the MCU operating voltage. Note however that if the LVR is enabled then R1 can be removed. Note: The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES to high. * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference.
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Instruction Set Summary
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to data memory with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory 1 1(1) 1 1 1(1) 1 1 1(1) 1 1(1) 1(1) Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C Description Instruction Cycle Flag Affected
Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC 1 1 1 1(1) 1(1) 1(1) 1 1 1 1(1) 1 Z Z Z Z Z Z Z Z Z Z Z
Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Clear bit of data memory Set bit of data memory 1(1) 1(1) None None Move data memory to ACC Move ACC to data memory Move immediate data to ACC 1 1(1) 1 None None None Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry 1 1(1) 1 1(1) 1 1(1) 1 1(1) None None C C None None C C Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory 1 1(1) 1 1(1) Z Z Z Z
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Mnemonic Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode 1 1(1) 1(1) 1 1 1 1(1) 1 1 None None None TO,PDF TO(4),PDF(4) TO(4),PDF(4) None None TO,PDF Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH 2(1) 2(1) None None Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) 2 2 2 2 None None None None None None None None None None None None None Description Instruction Cycle Flag Affected
x: Immediate data m: Data memory address A: Accumulator i: 0~7 number of bits addr: Program memory address O: Flag is affected -: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). : If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged. : and (2) : The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged.
(2)
(3) (1) (4)
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Instruction Definition
ADC A,[m] Description Operation Affected flag(s) TO 3/4 ADCM A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,x Description Operation Affected flag(s) TO 3/4 ADDM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Add data memory and carry to the accumulator The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. ACC ACC+[m]+C
Add the accumulator and carry to data memory The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. [m] ACC+[m]+C
Add data memory to the accumulator The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. ACC ACC+[m]
Add immediate data to the accumulator The contents of the accumulator and the specified data are added, leaving the result in the accumulator. ACC ACC+x
Add the accumulator to the data memory The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. [m] ACC+[m]
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AND A,[m] Description Operation Affected flag(s) TO 3/4 AND A,x Description Operation Affected flag(s) TO 3/4 ANDM A,[m] Description Operation Affected flag(s) TO 3/4 CALL addr Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical AND accumulator with data memory Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND [m]
Logical AND immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND x
Logical AND data memory with the accumulator Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. [m] ACC AND [m]
Subroutine call The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Stack Program Counter+1 Program Counter addr TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
CLR [m] Description Operation Affected flag(s)
Clear data memory The contents of the specified data memory are cleared to 0. [m] 00H TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
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CLR [m].i Description Operation Affected flag(s) TO 3/4 CLR WDT Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Clear bit of data memory The bit i of the specified data memory is cleared to 0. [m].i 0
Clear Watchdog Timer The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are cleared. WDT 00H PDF and TO 0 TO 0 PDF 0 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
CLR WDT1 Description
Preclear Watchdog Timer Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0* TO 0* PDF 0* OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
CLR WDT2 Description
Preclear Watchdog Timer Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0* TO 0* PDF 0* OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
CPL [m] Description Operation Affected flag(s)
Complement data memory Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. [m] [m] TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4
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CPLA [m] Description Complement data memory and place result in the accumulator Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. ACC [m] TO 3/4 DAA [m] Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4
Operation Affected flag(s)
Decimal-Adjust accumulator for addition The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ACC.7~ACC.4+AC1,C=C TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
DEC [m] Description Operation Affected flag(s)
Decrement data memory Data in the specified data memory is decremented by 1. [m] [m]-1 TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4
DECA [m] Description Operation Affected flag(s)
Decrement data memory and place result in the accumulator Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]-1 TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4
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HALT Description Enter power down mode This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PDF) is set and the WDT time-out bit (TO) is cleared. Program Counter Program Counter+1 PDF 1 TO 0 TO 0 INC [m] Description Operation Affected flag(s) TO 3/4 INCA [m] Description Operation Affected flag(s) TO 3/4 JMP addr Description Operation Affected flag(s) TO 3/4 MOV A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Directly jump The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. Program Counter addr PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 1 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
Increment data memory Data in the specified data memory is incremented by 1 [m] [m]+1
Increment data memory and place result in the accumulator Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]+1
Move data memory to the accumulator The contents of the specified data memory are copied to the accumulator. ACC [m]
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MOV A,x Description Operation Affected flag(s) TO 3/4 MOV [m],A Description Operation Affected flag(s) TO 3/4 NOP Description Operation Affected flag(s) TO 3/4 OR A,[m] Description Operation Affected flag(s) TO 3/4 OR A,x Description Operation Affected flag(s) TO 3/4 ORM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 No operation No operation is performed. Execution continues with the next instruction. Program Counter Program Counter+1 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move immediate data to the accumulator The 8-bit data specified by the code is loaded into the accumulator. ACC x
Move the accumulator to data memory The contents of the accumulator are copied to the specified data memory (one of the data memories). [m] ACC
Logical OR accumulator with data memory Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR [m]
Logical OR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR x
Logical OR data memory with the accumulator Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ACC OR [m]
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RET Description Operation Affected flag(s) TO 3/4 RET A,x Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Return from subroutine The program counter is restored from the stack. This is a 2-cycle instruction. Program Counter Stack
Return and place immediate data in the accumulator The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. Program Counter Stack ACC x TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RETI Description Operation
Return from interrupt The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit. Program Counter Stack EMI 1 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RL [m] Description Operation
Rotate data memory left The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RLA [m] Description Operation
Rotate data memory left and place result in the accumulator Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
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RLC [m] Description Operation Rotate data memory left through carry The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 C C [m].7 TO 3/4 RLCA [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Affected flag(s)
Rotate left through carry and place result in the accumulator Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 C C [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
RR [m] Description Operation
Rotate data memory right The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RRA [m] Description Operation
Rotate right and place result in the accumulator Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RRC [m] Description Operation
Rotate data memory right through carry The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 C C [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Affected flag(s)
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RRCA [m] Description Rotate right through carry and place result in the accumulator Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 C C [m].0 TO 3/4 SBC A,[m] Description Operation Affected flag(s) TO 3/4 SBCM A,[m] Description Operation Affected flag(s) TO 3/4 SDZ [m] Description PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. ACC ACC+[m]+C
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. [m] ACC+[m]+C
Skip if decrement data memory is 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, [m] ([m]-1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SDZA [m] Description
Decrement data memory and place result in ACC, skip if 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, ACC ([m]-1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
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SET [m] Description Operation Affected flag(s) TO 3/4 SET [m]. i Description Operation Affected flag(s) TO 3/4 SIZ [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Set data memory Each bit of the specified data memory is set to 1. [m] FFH
Set bit of data memory Bit i of the specified data memory is set to 1. [m].i 1
Skip if increment data memory is 0 The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, [m] ([m]+1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SIZA [m] Description
Increment data memory and place result in ACC, skip if 0 The contents of the specified data memory are incremented by 1. If the result is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, ACC ([m]+1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SNZ [m].i Description
Skip if bit i of the data memory is not 0 If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i0
Operation Affected flag(s)
TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
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SUB A,[m] Description Operation Affected flag(s) TO 3/4 SUBM A,[m] Description Operation Affected flag(s) TO 3/4 SUB A,x Description Operation Affected flag(s) TO 3/4 SWAP [m] Description Operation Affected flag(s) TO 3/4 SWAPA [m] Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+[m]+1
Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. [m] ACC+[m]+1
Subtract immediate data from the accumulator The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+x+1
Swap nibbles within the data memory The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged. [m].3~[m].0 [m].7~[m].4
Swap data memory and place result in the accumulator The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
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HT46RU66/HT46CU66
SZ [m] Description Skip if data memory is 0 If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TO 3/4 SZA [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move data memory to ACC, skip if 0 The contents of the specified data memory are copied to the accumulator. If the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TO 3/4 SZ [m].i Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Skip if bit i of the data memory is 0 If bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i=0
Operation Affected flag(s)
TO 3/4 TABRDC [m] Description Operation
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move the ROM code (current page) to TBLH and data memory The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
TABRDL [m] Description Operation
Move the ROM code (last page) to TBLH and data memory The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
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HT46RU66/HT46CU66
XOR A,[m] Description Operation Affected flag(s) TO 3/4 XORM A,[m] Description Operation Affected flag(s) TO 3/4 XOR A,x Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical XOR accumulator with data memory Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. ACC ACC XOR [m]
Logical XOR data memory with the accumulator Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected. [m] ACC XOR [m]
Logical XOR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected. ACC ACC XOR x
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Package Information
52-pin QFP (1414) Outline Dimensions
C D 39 27 G H
I 40 26 F A B E
52
14 K J 1 13
Symbol A B C D E F G H I J K a
Dimensions in mm Min. 17.3 13.9 17.3 13.9 3/4 3/4 2.5 3/4 3/4 0.73 0.1 0 Nom. 3/4 3/4 3/4 3/4 1 0.4 3/4 3/4 0.1 3/4 3/4 3/4 Max. 17.5 14.1 17.5 14.1 3/4 3/4 3.1 3.4 3/4 1.03 0.2 7
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HT46RU66/HT46CU66
56-pin SSOP (300mil) Outline Dimensions
56 A 1 C C'
29 B 28
G H a F
D E
Symbol A B C C D E F G H a
Dimensions in mil Min. 395 291 8 720 89 3/4 4 25 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 25 3/4 3/4 3/4 3/4 Max. 420 299 12 730 99 3/4 10 35 12 8
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HT46RU66/HT46CU66
100-pin QFP (1420) Outline Dimensions
C D 80 51 G H
I 81 50
F A B
E
100
31 K 1 30 a J
Symbol A B C D E F G H I J K a
Dimensions in mm Min. 18.50 13.90 24.50 19.90 3/4 3/4 2.50 3/4 3/4 1 0.10 0 Nom. 3/4 3/4 3/4 3/4 0.65 0.30 3/4 3/4 0.10 3/4 3/4 3/4 Max. 19.20 14.10 25.20 20.10 3/4 3/4 3.10 3.40 3/4 1.40 0.20 7
Rev. 1.00
64
July 10, 2006
HT46RU66/HT46CU66
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District, Shenzhen, China 518057 Tel: 0755-8616-9908, 8616-9308 Fax: 0755-8616-9533 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 010-6641-0030, 6641-7751, 6641-7752 Fax: 010-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 028-6653-6590 Fax: 028-6653-6591 Holmate Semiconductor, Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com
Copyright O 2006 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
65
July 10, 2006

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